Updated Console Logs (markdown)

JayDDee
2020-03-11 15:15:54 -04:00
parent 7268019ab5
commit d471fca2a7

@@ -6,16 +6,16 @@ but an effort was made to make them intuitive.
The application's sensitivity to CPU usage was a fcactor in log design. Perodic logs are not schedule
driven, the are opportunistic in that they look for opportunities to generate log with minimal impact.
Conditinal logs are avoided in high running code where testing the condition every iteration adds CPU ovedrhead.
Conditional logs are avoided in high running code where testing the condition every iteration adds CPU overhead.
The information is dense, the logs contain a lot of information in a small report. Every piece of data
has a puspose. Many fields can be correlated with other logs and fields and external data (pools, blochain
has a puspose. Many fields can be correlated with other logs and fields and external data (pools, blockchain
explorers, etc) to provide a more complete picture of actual mining performance.
The descriptions below will help understanding the significance of each field and how it can be used
to assess mining performance and help identify problems and aid troubleshooting.
to assess mining performance, help identify problems and aid troubleshooting.
For users not interest in details the --quiet option can be used.
For users not interested in details the --quiet option can be used.
### Colours
@@ -23,7 +23,7 @@ Somes logs and fields are colour coded based on their purpose or to highlight im
* Blue is used to report networking events, primarilly new jobs.
* Green is used to identify when a share has been accepted.
* Yellow is used when a share is stale or to warn of a minor error that may affect perforance.
* Yellow is used when a share is stale or to warn of a minor error that may affect performance.
* Red is a more serious error and is used when a share is rejected or when performance is affected or
may cause the miner to stop mining and exit.
@@ -49,8 +49,8 @@ take advantage of all the optimizations.
* Line 1: CPU brand and model
* Line 2: CPU hardware extensions available
* Line 3: Hardware extensions supported by the software build.
* Line 4: Extensions supported, to varying degrees, by the mining algorithm
* Line 3: Extensions supported by the software build
* Line 4: Extensions supported by the mining algorithm
* Line 5: Extensions to be used in the current session
Hardware extensions are divided into 3 classes, SIMD, AES and SHA. Each class can have multiple levels.
@@ -59,16 +59,16 @@ each class is displayed although lower ranking features may also exist and be av
have significant improvements and not all combinations are avalable in binary format for Windows.
### SIMD vector support
* SSE2: minimum for 128 bit integer vector support, first available on Intel Core2.
* SSE2: Minimum for 128 bit integer vector support, first available on Intel Core2.
* SSSE3: Some additional instructions for 128 bit integer vectors, not very significant.
* SSE4.2: More 128 bit vector instructions, also not very significant.
* AVX: Initial support for 256 bit vectors but no integer support.
* AVX2: minimum level for 256 bit integer vector support, first available on Intel Haswell and AMD Ryzen.
* AVX512: a suite of seperate extensions that provide 512 bit vector support, first available on
Intel Cascade Lake X HEDT CPUs.
* AVX: Supersedes all SSE versions. Provides initial support for 256 bit vectors but not integer support.
* AVX2: Minimum level for 256 bit integer vector support, first available on Intel Haswell and AMD Ryzen.
* AVX512: A suite of seperate extensions that provide 512 bit vector support. Cpuminer-opt support requires
AVX512F, AVX512VL, AVX512DQ, & AVX512BW, first available omn Intel Cascade lake X HEDT CPUs.
### AES encryption and decryption, aka AES_NI
* AES: basic hardware AES support performs AES operations with a single instruction, also requires SSE2,
* AES: Basic hardware AES support performs AES operations with a single instruction, also requires SSE2,
first available on Intel Westmere.
* VAES: Vectored AES, supports 4 parallel AES operations with a single instruction, first available on Intel
Icelake. Also requires AVX512F.