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JayDDee
2020-02-08 02:46:52 -05:00
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@@ -414,15 +414,40 @@ take advantage of all the algo optimizations.
`
CPU: AMD Ryzen 7 1700 Eight-Core Processor .
SW built on Feb 7 2020 with GCC 7.4.0.
SW built on Feb 8 2020 with GCC 7.4.0.
CPU features: AVX2 AES SHA
SW features: AVX2 AES SHA
Algo features: AVX512
Algo features: AVX512 VAES
Starting miner with AVX2 AES...
`
Starting miner with AVX2...
Line 1: CPU brand and model
Line 2: CPU hardware extensions available
Line 3: Hardware extensions supported by the software build.
Line 4: Extensions supported, to varying degrees, by the mining algorithm
Line 5: Extensions to be used in the current session
Hardware extensions are divided into 3 classes, SIMD, AES and SHA. There are multiple levels in each clash.
Each provides additional CPU instructions more complex operations.
* Simd vector support
SSE2: minimum for 128 bit integer vector support, first available on Intel core2.
SSSE3: Some additional instructions for 128 bit integer vectors, not very significant.
SSE4.2: More 128 bit vector instructions, also not very significant.
AVX: Initial support for 256 bit vectors but no interger support.
AVX2: minimum level for 256 bit integer vector support, first available on Intel Haswell.
AVX512: a suite of seperate extensions that provide 512 bit integer vector support, first available on
Intel Cascade Lake X HEDT CPUs.
* AES encryption and decryption, aka AES_NI
AES: basic hardware AES support performs AES operations with a single instruction, also requires SSE2,
first available on Intel Westmere.
VAES: vectored AES, supports 4 parallel AES operation with a single instruction, first available on Intel
Icelake.
* SHA encryption and decryption, aka SHA_NI
SHA supports basic SHA-256 operations with a single instruction, also requires SSE2. First available
on Intel Goldont but not widely avaiable until AMD Ryzen and Intel Icelake.
### New stratum, block job report