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Updated Console Logs (markdown)

JayDDee
2020-03-02 00:06:18 -05:00
parent cdc9db9c17
commit fae4d36c18
1 changed files with 15 additions and 15 deletions
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Console-Logs.md

@@ -15,7 +15,7 @@ and provide estimates.
## Start up ## Start up
The startup messages are very important to ensure best performmance. In particular The startup messages are very important to ensure best performance. In particular
the features lists ensure the software is built for the CPU architecture and can the features lists ensure the software is built for the CPU architecture and can
take advantage of all the algo optimizations. take advantage of all the algo optimizations.
@@ -32,11 +32,11 @@ take advantage of all the algo optimizations.
`Starting miner with AVX2 AES...` `Starting miner with AVX2 AES...`
Line 1: CPU brand and model * Line 1: CPU brand and model
Line 2: CPU hardware extensions available * Line 2: CPU hardware extensions available
Line 3: Hardware extensions supported by the software build. * Line 3: Hardware extensions supported by the software build.
Line 4: Extensions supported, to varying degrees, by the mining algorithm * Line 4: Extensions supported, to varying degrees, by the mining algorithm
Line 5: Extensions to be used in the current session * Line 5: Extensions to be used in the current session
Hardware extensions are divided into 3 classes, SIMD, AES and SHA. There are multiple levels in each clash. Hardware extensions are divided into 3 classes, SIMD, AES and SHA. There are multiple levels in each clash.
Each provides additional CPU instructions and more complex operations. Only the highest ranked feature in Each provides additional CPU instructions and more complex operations. Only the highest ranked feature in
@@ -44,22 +44,22 @@ each class is displayed although lower ranking features may also exist and be av
have significant improvements and not all combinations are avalable in binary format for Windows. have significant improvements and not all combinations are avalable in binary format for Windows.
### SIMD vector support ### SIMD vector support
SSE2: minimum for 128 bit integer vector support, first available on Intel Core2. * SSE2: minimum for 128 bit integer vector support, first available on Intel Core2.
SSSE3: Some additional instructions for 128 bit integer vectors, not very significant. * SSSE3: Some additional instructions for 128 bit integer vectors, not very significant.
SSE4.2: More 128 bit vector instructions, also not very significant. * SSE4.2: More 128 bit vector instructions, also not very significant.
AVX: Initial support for 256 bit vectors but no integer support. * AVX: Initial support for 256 bit vectors but no integer support.
AVX2: minimum level for 256 bit integer vector support, first available on Intel Haswell amd AMD Ryzen. * AVX2: minimum level for 256 bit integer vector support, first available on Intel Haswell amd AMD Ryzen.
AVX512: a suite of seperate extensions that provide 512 bit integer vector support, first available on * AVX512: a suite of seperate extensions that provide 512 bit integer vector support, first available on
Intel Cascade Lake X HEDT CPUs. Intel Cascade Lake X HEDT CPUs.
### AES encryption and decryption, aka AES_NI ### AES encryption and decryption, aka AES_NI
AES: basic hardware AES support performs AES operations with a single instruction, also requires SSE2, * AES: basic hardware AES support performs AES operations with a single instruction, also requires SSE2,
first available on Intel Westmere. first available on Intel Westmere.
VAES: Vectored AES, supports 4 parallel AES operations with a single instruction, first available on Intel * VAES: Vectored AES, supports 4 parallel AES operations with a single instruction, first available on Intel
Icelake. Also requires AVX512F. Icelake. Also requires AVX512F.
### SHA encryption and decryption, aka SHA_NI ### SHA encryption and decryption, aka SHA_NI
SHA supports basic SHA-256 operations with a single instruction, also requires SSE2. First available * SHA supports basic SHA-256 operations with a single instruction, also requires SSE2. First available
on Intel Goldmont but not widely avaiable until AMD Ryzen and Intel Icelake. on Intel Goldmont but not widely avaiable until AMD Ryzen and Intel Icelake.
Some other messages are displayed based on options such as stratum connection, API enabled, CPU affinity etc. Some other messages are displayed based on options such as stratum connection, API enabled, CPU affinity etc.