From 748f193c9a37c3eae41edf7f28c3795cd93fea87 Mon Sep 17 00:00:00 2001 From: JayDDee Date: Sun, 13 Dec 2020 15:10:45 -0500 Subject: [PATCH] Updated Console Logs (markdown) --- Console-Logs.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Console-Logs.md b/Console-Logs.md index 82189db..41cc14b 100644 --- a/Console-Logs.md +++ b/Console-Logs.md @@ -70,13 +70,14 @@ have significant improvements and not all combinations are avalable in binary fo * AVX: Supersedes all SSE versions. Provides initial support for 256 bit vectors but not integer support. * AVX2: Minimum level for 256 bit integer vector support, first available on Intel Haswell and AMD Ryzen. * AVX512: A suite of seperate extensions that provide 512 bit vector support. Cpuminer-opt support requires -AVX512F, AVX512VL, AVX512DQ, & AVX512BW, first available on Intel Cascade Lake X HEDT CPUs. +AVX512F, AVX512VL, AVX512DQ, & AVX512BW, first available on Intel Skylake X HEDT CPUs. ### AES encryption and decryption, aka AES_NI * AES: Basic hardware AES support performs AES operations with a single instruction, also requires SSE2, first available on Intel Westmere. * VAES: Vectored AES, supports 4 parallel AES operations with a single instruction, first available on Intel - Icelake. Also requires AVX512F. + Icelake. Also requires AVX512F. AMD Zen3 supports 256 bit VAES only (2-way parallel) without AVX512F. + The Intel specification states 256 bit VAES is only avaiable on CPUs with AVX512VL & AVX512F. ### SHA encryption and decryption, aka SHA_NI * SHA supports basic SHA-256 operations with a single instruction, also requires SSE2. First available