mirror of
https://github.com/JayDDee/cpuminer-opt.git
synced 2025-09-17 23:44:27 +00:00
680 lines
23 KiB
C
680 lines
23 KiB
C
#if !defined(SIMD_256_H__)
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#define SIMD_256_H__ 1
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#if defined(__AVX__)
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/////////////////////////////////////////////////////////////////////
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//
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// AVX2 256 bit vectors
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//
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// Basic support for 256 bit vectors is available with AVX but integer
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// support requires AVX2.
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// Some 256 bit vector utilities require AVX512 or have more efficient
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// AVX512 implementations. They will be selected automatically but their use
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// is limited because 256 bit vectors are less likely to be used when 512
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// is available.
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//
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// All SIMD constant macros are actually functions containing executable
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// code and therefore can't be used as compile time initializers.
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#define m256_zero _mm256_setzero_si256()
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#define m256_one_256 \
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_mm256_inserti128_si256( _mm256_castsi128_si256( m128_one_128 ), \
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m128_zero, 1 )
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#define m256_one_128 \
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_mm256_inserti128_si256( _mm256_castsi128_si256( m128_one_128 ), \
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m128_one_128, 1 )
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// set instructions load memory resident constants, this avoids mem.
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// cost 4 pinsert + 1 vinsert, estimate 8 clocks latency.
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#define m256_const_64( i3, i2, i1, i0 ) \
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_mm256_inserti128_si256( _mm256_castsi128_si256( m128_const_64( i1, i0 ) ), \
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m128_const_64( i3, i2 ), 1 )
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static inline __m256i m256_const1_64( uint64_t i )
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{
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register __m128i a;
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asm( "movq %1, %0\n\t"
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: "=x"(a)
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: "r"(i) );
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return _mm256_broadcastq_epi64( a );
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}
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#if defined(__AVX2__)
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// Don't call the frunction directly, use the macro to make appear like
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// a constant identifier instead of a function.
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// __m256i foo = m256_one_64;
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static inline __m256i m256_one_64_fn()
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{
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register uint64_t one = 1;
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register __m128i a;
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asm( "movq %1, %0\n\t"
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: "=x" (a)
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: "r" (one) );
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return _mm256_broadcastq_epi64( a );
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}
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#define m256_one_64 m256_one_64_fn()
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static inline __m256i m256_one_32_fn()
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{
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register uint64_t one = 0x0000000100000001;
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register __m128i a;
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asm( "movq %1, %0\n\t"
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: "=x" (a)
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: "r" (one) );
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return _mm256_broadcastq_epi64( a );
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}
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#define m256_one_32 m256_one_32_fn()
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static inline __m256i m256_one_16_fn()
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{
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register uint64_t one = 0x0001000100010001;
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register __m128i a;
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asm( "movq %1, %0\n\t"
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: "=x" (a)
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: "r" (one) );
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return _mm256_broadcastq_epi64( a );
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}
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#define m256_one_16 m256_one_16_fn()
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static inline __m256i m256_one_8_fn()
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{
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register uint64_t one = 0x0101010101010101;
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register __m128i a;
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asm( "movq %1, %0\n\t"
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: "=x" (a)
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: "r" (one) );
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return _mm256_broadcastq_epi64( a );
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}
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#define m256_one_8 m256_one_8_fn()
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static inline __m256i m256_neg1_fn()
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{
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register __m256i a;
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asm( "vpcmpeqq %0, %0, %0\n\t"
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: "=x"(a) );
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return a;
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}
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#define m256_neg1 m256_neg1_fn()
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#else // AVX
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#define m256_one_64 _mm256_set1_epi64x( 1ULL )
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#define m256_one_32 _mm256_set1_epi64x( 0x0000000100000001ULL )
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#define m256_one_16 _mm256_set1_epi64x( 0x0001000100010001ULL )
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#define m256_one_8 _mm256_set1_epi64x( 0x0101010101010101ULL )
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// AVX doesn't have inserti128 but insertf128 will do.
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static inline __m256i m256_neg1_fn()
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{
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__m128i a = m128_neg1;
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return _mm256_insertf128_si256( _mm256_castsi128_si256( a ), a, 1 );
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}
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#define m256_neg1 m256_neg1_fn()
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#endif // AVX2 else AVX
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//
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// Vector size conversion.
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//
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// Allows operations on either or both halves of a 256 bit vector serially.
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// Handy for parallel AES.
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// Caveats when writing:
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// _mm256_castsi256_si128 is free and without side effects.
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// _mm256_castsi128_si256 is also free but leaves the high half
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// undefined. That's ok if the hi half will be subseqnently assigned.
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// If assigning both, do lo first, If assigning only 1, use
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// _mm256_inserti128_si256.
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//
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#define mm128_extr_lo128_256( a ) _mm256_castsi256_si128( a )
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#define mm128_extr_hi128_256( a ) _mm256_extracti128_si256( a, 1 )
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// Extract integers from 256 bit vector, ineficient, avoid if possible..
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#define mm256_extr_4x64( a0, a1, a2, a3, src ) \
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do { \
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__m128i hi = _mm256_extracti128_si256( src, 1 ); \
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a0 = mm256_mov256_64( src ); \
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a1 = _mm_extract_epi64( _mm256_castsi256_si128( src ), 1 ); \
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a2 = _mm_extract_epi64( hi, 0 ); \
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a3 = _mm_extract_epi64( hi, 1 ); \
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} while(0)
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#define mm256_extr_8x32( a0, a1, a2, a3, a4, a5, a6, a7, src ) \
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do { \
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__m128i hi = _mm256_extracti128_si256( src, 1 ); \
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a0 = mm256_mov256_32( src ); \
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a1 = _mm_extract_epi32( _mm256_castsi256_si128( src ), 1 ); \
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a2 = _mm_extract_epi32( _mm256_castsi256_si128( src ), 2 ); \
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a3 = _mm_extract_epi32( _mm256_castsi256_si128( src ), 3 ); \
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a4 = mm128_mov128_32( hi ); \
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a5 = _mm_extract_epi32( hi, 1 ); \
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a6 = _mm_extract_epi32( hi, 2 ); \
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a7 = _mm_extract_epi32( hi, 3 ); \
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} while(0)
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// concatenate two 128 bit vectors into one 256 bit vector: { hi, lo }
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#define mm256_concat_128( hi, lo ) \
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_mm256_inserti128_si256( _mm256_castsi128_si256( lo ), hi, 1 )
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// Move integer to lower bits of vector, upper bits set to zero.
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static inline __m256i mm256_mov64_256( uint64_t n )
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{
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register __m128i a;
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asm( "movq %1, %0\n\t"
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: "=x" (a)
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: "r" (n) );
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return _mm256_castsi128_si256( a );
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}
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static inline __m256i mm256_mov32_256( uint32_t n )
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{
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register __m128i a;
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asm( "movd %1, %0\n\t"
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: "=x" (a)
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: "r" (n) );
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return _mm256_castsi128_si256( a );
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}
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// Move lo bits of vector to integer, hi bits are truncated.
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#define mm256_mov256_64( a ) mm128_mov128_64( _mm256_castsi256_si128( a ) )
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#define mm256_mov256_32( a ) mm128_mov128_32( _mm256_castsi256_si128( a ) )
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// Horizontal vector testing
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#if defined(__AVX2__)
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#define mm256_allbits0( a ) _mm256_testz_si256( a, a )
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#define mm256_allbits1( a ) _mm256_testc_si256( a, m256_neg1 )
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#define mm256_allbitsne( a ) _mm256_testnzc_si256( a, m256_neg1 )
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#define mm256_anybits0 mm256_allbitsne
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#define mm256_anybits1 mm256_allbitsne
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#else // AVX
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// Bit-wise test of entire vector, useful to test results of cmp.
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#define mm256_anybits0( a ) \
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( (uint128_t)mm128_extr_hi128_256( a ) \
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| (uint128_t)mm128_extr_lo128_256( a ) )
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#define mm256_anybits1( a ) \
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( ( (uint128_t)mm128_extr_hi128_256( a ) + 1 ) \
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| ( (uint128_t)mm128_extr_lo128_256( a ) + 1 ) )
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#define mm256_allbits0_256( a ) ( !mm256_anybits1(a) )
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#define mm256_allbits1_256( a ) ( !mm256_anybits0(a) )
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#endif // AVX2 else AVX
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// Parallel AES, for when x is expected to be in a 256 bit register.
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// Use same 128 bit key.
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#define mm256_aesenc_2x128( x, k ) \
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mm256_concat_128( _mm_aesenc_si128( mm128_extr_hi128_256( x ), k ), \
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_mm_aesenc_si128( mm128_extr_lo128_256( x ), k ) )
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#define mm256_paesenc_2x128( y, x, k ) do \
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{ \
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__m128i *X = (__m128i*)x; \
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__m128i *Y = (__m128i*)y; \
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Y[0] = _mm_aesenc_si128( X[0], k ); \
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Y[1] = _mm_aesenc_si128( X[1], k ); \
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} while(0);
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//
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// Pointer casting
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// p = any aligned pointer
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// returns p as pointer to vector type, not very useful
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#define castp_m256i(p) ((__m256i*)(p))
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// p = any aligned pointer
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// returns *p, watch your pointer arithmetic
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#define cast_m256i(p) (*((__m256i*)(p)))
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// p = any aligned pointer, i = scaled array index
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// returns value p[i]
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#define casti_m256i(p,i) (((__m256i*)(p))[(i)])
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// p = any aligned pointer, o = scaled offset
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// returns pointer p+o
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#define casto_m256i(p,o) (((__m256i*)(p))+(o))
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// Gather scatter
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#define mm256_gather_64( d, s0, s1, s2, s3 ) \
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((uint64_t*)(d))[0] = (uint64_t)(s0); \
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((uint64_t*)(d))[1] = (uint64_t)(s1); \
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((uint64_t*)(d))[2] = (uint64_t)(s2); \
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((uint64_t*)(d))[3] = (uint64_t)(s3);
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#define mm256_gather_32( d, s0, s1, s2, s3, s4, s5, s6, s7 ) \
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((uint32_t*)(d))[0] = (uint32_t)(s0); \
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((uint32_t*)(d))[1] = (uint32_t)(s1); \
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((uint32_t*)(d))[2] = (uint32_t)(s2); \
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((uint32_t*)(d))[3] = (uint32_t)(s3); \
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((uint32_t*)(d))[4] = (uint32_t)(s4); \
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((uint32_t*)(d))[5] = (uint32_t)(s5); \
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((uint32_t*)(d))[6] = (uint32_t)(s6); \
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((uint32_t*)(d))[7] = (uint32_t)(s7);
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// Scatter data from contiguous memory.
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// All arguments are pointers
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#define mm256_scatter_64( d0, d1, d2, d3, s ) \
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*((uint64_t*)(d0)) = ((uint64_t*)(s))[0]; \
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*((uint64_t*)(d1)) = ((uint64_t*)(s))[1]; \
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*((uint64_t*)(d2)) = ((uint64_t*)(s))[2]; \
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*((uint64_t*)(d3)) = ((uint64_t*)(s))[3];
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#define mm256_scatter_32( d0, d1, d2, d3, d4, d5, d6, d7, s ) \
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*((uint32_t*)(d0)) = ((uint32_t*)(s))[0]; \
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*((uint32_t*)(d1)) = ((uint32_t*)(s))[1]; \
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*((uint32_t*)(d2)) = ((uint32_t*)(s))[2]; \
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*((uint32_t*)(d3)) = ((uint32_t*)(s))[3]; \
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*((uint32_t*)(d4)) = ((uint32_t*)(s))[4]; \
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*((uint32_t*)(d5)) = ((uint32_t*)(s))[5]; \
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*((uint32_t*)(d6)) = ((uint32_t*)(s))[6]; \
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*((uint32_t*)(d7)) = ((uint32_t*)(s))[7];
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//
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// Memory functions
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// n = number of 256 bit (32 byte) vectors
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static inline void memset_zero_256( __m256i *dst, const int n )
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{ for ( int i = 0; i < n; i++ ) dst[i] = m256_zero; }
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static inline void memset_256( __m256i *dst, const __m256i a, const int n )
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{ for ( int i = 0; i < n; i++ ) dst[i] = a; }
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static inline void memcpy_256( __m256i *dst, const __m256i *src, const int n )
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{ for ( int i = 0; i < n; i ++ ) dst[i] = src[i]; }
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///////////////////////////////
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//
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// AVX2 needed from now on.
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//
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#if defined(__AVX2__)
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//
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// Basic operations without SIMD equivalent
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// Bitwise not ( ~x )
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#define mm256_not( x ) _mm256_xor_si256( (x), m256_neg1 ) \
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// Unary negation of each element ( -a )
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#define mm256_negate_64( a ) _mm256_sub_epi64( m256_zero, a )
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#define mm256_negate_32( a ) _mm256_sub_epi32( m256_zero, a )
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#define mm256_negate_16( a ) _mm256_sub_epi16( m256_zero, a )
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// Add 4 values, fewer dependencies than sequential addition.
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#define mm256_add4_64( a, b, c, d ) \
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_mm256_add_epi64( _mm256_add_epi64( a, b ), _mm256_add_epi64( c, d ) )
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#define mm256_add4_32( a, b, c, d ) \
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_mm256_add_epi32( _mm256_add_epi32( a, b ), _mm256_add_epi32( c, d ) )
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#define mm256_add4_16( a, b, c, d ) \
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_mm256_add_epi16( _mm256_add_epi16( a, b ), _mm256_add_epi16( c, d ) )
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#define mm256_add4_8( a, b, c, d ) \
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_mm256_add_epi8( _mm256_add_epi8( a, b ), _mm256_add_epi8( c, d ) )
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#define mm256_xor4( a, b, c, d ) \
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_mm256_xor_si256( _mm256_xor_si256( a, b ), _mm256_xor_si256( c, d ) )
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//
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// Bit rotations.
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//
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// The only bit shift for more than 64 bits is with __int128.
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//
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// AVX512 has bit rotate for 256 bit vectors with 64 or 32 bit elements
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// but is of little value
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//
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// Rotate each element of v by c bits
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#define mm256_ror_64( v, c ) \
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_mm256_or_si256( _mm256_srli_epi64( v, c ), \
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_mm256_slli_epi64( v, 64-(c) ) )
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#define mm256_rol_64( v, c ) \
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_mm256_or_si256( _mm256_slli_epi64( v, c ), \
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_mm256_srli_epi64( v, 64-(c) ) )
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#define mm256_ror_32( v, c ) \
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_mm256_or_si256( _mm256_srli_epi32( v, c ), \
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_mm256_slli_epi32( v, 32-(c) ) )
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#define mm256_rol_32( v, c ) \
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_mm256_or_si256( _mm256_slli_epi32( v, c ), \
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_mm256_srli_epi32( v, 32-(c) ) )
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#define mm256_ror_16( v, c ) \
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_mm256_or_si256( _mm256_srli_epi16( v, c ), \
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_mm256_slli_epi16( v, 16-(c) ) )
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#define mm256_rol_16( v, c ) \
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_mm256_or_si256( _mm256_slli_epi16( v, c ), \
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_mm256_srli_epi16( v, 16-(c) ) )
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// Rotate bits in each element of v by the amount in corresponding element of
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// index vector c
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#define mm256_rorv_64( v, c ) \
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_mm256_or_si256( \
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_mm256_srlv_epi64( v, c ), \
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_mm256_sllv_epi64( v, _mm256_sub_epi64( \
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_mm256_set1_epi64x( 64 ), c ) ) )
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#define mm256_rolv_64( v, c ) \
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_mm256_or_si256( \
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_mm256_sllv_epi64( v, c ), \
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_mm256_srlv_epi64( v, _mm256_sub_epi64( \
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_mm256_set1_epi64x( 64 ), c ) ) )
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#define mm256_rorv_32( v, c ) \
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_mm256_or_si256( \
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_mm256_srlv_epi32( v, c ), \
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_mm256_sllv_epi32( v, _mm256_sub_epi32( \
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_mm256_set1_epi32( 32 ), c ) ) )
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#define mm256_rolv_32( v, c ) \
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_mm256_or_si256( \
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_mm256_sllv_epi32( v, c ), \
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_mm256_srlv_epi32( v, _mm256_sub_epi32( \
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_mm256_set1_epi32( 32 ), c ) ) )
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// AVX512 can do 16 bit elements.
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//
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// Rotate elements accross all lanes.
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//
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// AVX2 has no full vector permute for elements less than 32 bits.
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// AVX512 has finer granularity full vector permutes.
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// Swap 128 bit elements in 256 bit vector.
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#define mm256_swap_128( v ) _mm256_permute4x64_epi64( v, 0x4e )
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// Rotate 256 bit vector by one 64 bit element
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#define mm256_ror_1x64( v ) _mm256_permute4x64_epi64( v, 0x39 )
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#define mm256_rol_1x64( v ) _mm256_permute4x64_epi64( v, 0x93 )
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// A little faster with avx512
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// Rotate 256 bit vector by one 32 bit element.
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#define mm256_ror_1x32( v ) \
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_mm256_permutevar8x32_epi32( v, \
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m256_const_64( 0x0000000000000007, 0x0000000600000005, \
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0x0000000400000003, 0x0000000200000001 )
|
|
|
|
#define mm256_rol_1x32( v ) \
|
|
_mm256_permutevar8x32_epi32( v, \
|
|
m256_const_64( 0x0000000600000005, 0x0000000400000003, \
|
|
0x0000000200000001, 0x0000000000000007 )
|
|
|
|
// Rotate 256 bit vector by three 32 bit elements (96 bits).
|
|
#define mm256_ror_3x32( v ) \
|
|
_mm256_permutevar8x32_epi32( v, \
|
|
m256_const_64( 0x0000000200000001, 0x0000000000000007, \
|
|
0x0000000600000005, 0x0000000400000003 )
|
|
|
|
#define mm256_rol_3x32( v ) \
|
|
_mm256_permutevar8x32_epi32( v, \
|
|
m256_const_64( 0x0000000400000003, 0x0000000200000001, \
|
|
0x0000000000000007, 0x0000000600000005 )
|
|
|
|
// AVX512 can do 16 & 8 bit elements.
|
|
#if defined(__AVX512VL__)
|
|
|
|
// Rotate 256 bit vector by one 16 bit element.
|
|
#define mm256_ror_1x16( v ) \
|
|
_mm256_permutexvar_epi16( m256_const_64( \
|
|
0x0000000f000e000d, 0x000c000b000a0009, \
|
|
0x0008000700060005, 0x0004000300020001 ), v )
|
|
|
|
#define mm256_rol_1x16( v ) \
|
|
_mm256_permutexvar_epi16( m256_const_64( \
|
|
0x000e000d000c000b, 0x000a000900080007, \
|
|
0x0006000500040003, 0x000200010000000f ), v )
|
|
|
|
// Rotate 256 bit vector by one byte.
|
|
#define mm256_ror_1x8( v ) m256_const_64( \
|
|
0x001f1e1d1c1b1a19, 0x1817161514131211, \
|
|
0x100f0e0d0c0b0a09, 0x0807060504030201 )
|
|
|
|
#define mm256_rol_1x8( v ) m256_const_64( \
|
|
0x1e1d1c1b1a191817, 0x161514131211100f, \
|
|
0x0e0d0c0b0a090807, 0x060504030201001f )
|
|
|
|
#endif // AVX512
|
|
|
|
//
|
|
// Rotate elements within lanes of 256 bit vector.
|
|
|
|
// Swap 64 bit elements in each 128 bit lane.
|
|
#define mm256_swap64_128( v ) _mm256_shuffle_epi32( v, 0x4e )
|
|
|
|
// Rotate each 128 bit lane by one 32 bit element.
|
|
#define mm256_ror1x32_128( v ) _mm256_shuffle_epi32( v, 0x39 )
|
|
#define mm256_rol1x32_128( v ) _mm256_shuffle_epi32( v, 0x93 )
|
|
|
|
// Rotate each 128 bit lane by one 16 bit element.
|
|
#define mm256_ror1x16_128( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x01000f0e0d0c0b0a, \
|
|
0x0908070605040302, \
|
|
0x01000f0e0d0c0b0a, \
|
|
0x0908070605040302 ) )
|
|
#define mm256_rol1x16_128( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x0d0c0b0a09080706, \
|
|
0x0504030201000f0e, \
|
|
0x0d0c0b0a09080706, \
|
|
0x0504030201000f0e ) )
|
|
|
|
// Rotate each 128 bit lane by one byte
|
|
#define mm256_ror1x8_128( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x000f0e0d0c0b0a09, \
|
|
0x0807060504030201, \
|
|
0x000f0e0d0c0b0a09, \
|
|
0x0807060504030201 ) )
|
|
#define mm256_rol1x8_128( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x0c0b0a09080f0e0d, \
|
|
0x0504030201000706, \
|
|
0x0d0c0b0a09080f0e, \
|
|
0x0504030201000706 ) )
|
|
|
|
// Rotate each 128 bit lane by c bytes.
|
|
#define mm256_bror_128( v, c ) \
|
|
_mm256_or_si256( _mm256_bsrli_epi128( v, c ), \
|
|
_mm256_bslli_epi128( v, 16-(c) ) )
|
|
#define mm256_brol_128( v, c ) \
|
|
_mm256_or_si256( _mm256_bslli_epi128( v, c ), \
|
|
_mm256_bsrli_epi128( v, 16-(c) ) )
|
|
|
|
// Swap 32 bit elements in each 64 bit lane
|
|
#define mm256_swap32_64( v ) _mm256_shuffle_epi32( v, 0xb1 )
|
|
|
|
#define mm256_ror1x16_64( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x09080f0e0d0c0b0a, \
|
|
0x0100070605040302, \
|
|
0x09080f0e0d0c0b0a, \
|
|
0x0100070605040302 ) )
|
|
#define mm256_rol1x16_64( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x0d0c0b0a09080f0e, \
|
|
0x0504030201000706, \
|
|
0x0d0c0b0a09080f0e, \
|
|
0x0504030201000706 ))
|
|
|
|
#define mm256_ror1x8_64( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x080f0e0d0c0b0a09, \
|
|
0x0007060504030201, \
|
|
0x080f0e0d0c0b0a09, \
|
|
0x0007060504030201 ))
|
|
#define mm256_rol1x8_64( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x0e0d0c0b0a09080f, \
|
|
0x0605040302010007, \
|
|
0x0e0d0c0b0a09080f, \
|
|
0x0605040302010007 ) )
|
|
|
|
#define mm256_ror3x8_64( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x0a09080f0e0d0c0b, \
|
|
0x0201000706050403, \
|
|
0x0a09080f0e0d0c0b, \
|
|
0x0201000706050403 ) )
|
|
#define mm256_rol3x8_64( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x0c0b0a09080f0e0d, \
|
|
0x0403020100070605, \
|
|
0x0c0b0a09080f0e0d, \
|
|
0x0403020100070605 ) )
|
|
|
|
// Swap 16 bit elements in each 32 bit lane
|
|
#define mm256_swap16_32( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x0b0a09080f0e0d0c, \
|
|
0x0302010007060504, \
|
|
0x0b0a09080f0e0d0c, \
|
|
0x0302010007060504 )
|
|
|
|
//
|
|
// Swap bytes in vector elements, endian bswap.
|
|
#define mm256_bswap_64( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x08090a0b0c0d0e0f, \
|
|
0x0001020304050607, \
|
|
0x08090a0b0c0d0e0f, \
|
|
0x0001020304050607 ) )
|
|
|
|
#define mm256_bswap_32( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x0c0d0e0f08090a0b, \
|
|
0x0405060700010203, \
|
|
0x0c0d0e0f08090a0b, \
|
|
0x0405060700010203 ) )
|
|
|
|
#define mm256_bswap_16( v ) \
|
|
_mm256_shuffle_epi8( v, m256_const_64( 0x0e0f0c0d0a0b0809, \
|
|
0x0607040502030001, \
|
|
0x0e0f0c0d0a0b0809, \
|
|
0x0607040502030001 ) )
|
|
|
|
// 8 byte qword * 8 qwords * 4 lanes = 256 bytes
|
|
#define mm256_block_bswap_64( d, s ) do \
|
|
{ \
|
|
__m256i ctl = m256_const_64( 0x08090a0b0c0d0e0f, 0x0001020304050607, \
|
|
0x08090a0b0c0d0e0f, 0x0001020304050607 ); \
|
|
casti_m256i( d, 0 ) = _mm256_shuffle_epi8( casti_m256i( s, 0 ), ctl ); \
|
|
casti_m256i( d, 1 ) = _mm256_shuffle_epi8( casti_m256i( s, 1 ), ctl ); \
|
|
casti_m256i( d, 2 ) = _mm256_shuffle_epi8( casti_m256i( s, 2 ), ctl ); \
|
|
casti_m256i( d, 3 ) = _mm256_shuffle_epi8( casti_m256i( s, 3 ), ctl ); \
|
|
casti_m256i( d, 4 ) = _mm256_shuffle_epi8( casti_m256i( s, 4 ), ctl ); \
|
|
casti_m256i( d, 5 ) = _mm256_shuffle_epi8( casti_m256i( s, 5 ), ctl ); \
|
|
casti_m256i( d, 6 ) = _mm256_shuffle_epi8( casti_m256i( s, 6 ), ctl ); \
|
|
casti_m256i( d, 7 ) = _mm256_shuffle_epi8( casti_m256i( s, 7 ), ctl ); \
|
|
} while(0)
|
|
|
|
// 4 byte dword * 8 dwords * 8 lanes = 256 bytes
|
|
#define mm256_block_bswap_32( d, s ) do \
|
|
{ \
|
|
__m256i ctl = m256_const_64( 0x0c0d0e0f08090a0b, 0x0405060700010203, \
|
|
0x0c0d0e0f08090a0b, 0x0405060700010203 ); \
|
|
casti_m256i( d, 0 ) = _mm256_shuffle_epi8( casti_m256i( s, 0 ), ctl ); \
|
|
casti_m256i( d, 1 ) = _mm256_shuffle_epi8( casti_m256i( s, 1 ), ctl ); \
|
|
casti_m256i( d, 2 ) = _mm256_shuffle_epi8( casti_m256i( s, 2 ), ctl ); \
|
|
casti_m256i( d, 3 ) = _mm256_shuffle_epi8( casti_m256i( s, 3 ), ctl ); \
|
|
casti_m256i( d, 4 ) = _mm256_shuffle_epi8( casti_m256i( s, 4 ), ctl ); \
|
|
casti_m256i( d, 5 ) = _mm256_shuffle_epi8( casti_m256i( s, 5 ), ctl ); \
|
|
casti_m256i( d, 6 ) = _mm256_shuffle_epi8( casti_m256i( s, 6 ), ctl ); \
|
|
casti_m256i( d, 7 ) = _mm256_shuffle_epi8( casti_m256i( s, 7 ), ctl ); \
|
|
} while(0)
|
|
|
|
//
|
|
// Rotate two concatenated 256 bit vectors as one 512 bit vector by specified
|
|
// number of elements. Rotate is done in place, source arguments are
|
|
// overwritten.
|
|
// Some of these can use permute but appears to be slower. Maybe a Ryzen
|
|
// issue
|
|
|
|
#define mm256_swap256_512 (v1, v2) \
|
|
v1 = _mm256_xor_si256(v1, v2); \
|
|
v2 = _mm256_xor_si256(v1, v2); \
|
|
v1 = _mm256_xor_si256(v1, v2);
|
|
|
|
#define mm256_ror1x128_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 16 ); \
|
|
v1 = _mm256_alignr_epi8( v2, v1, 16 ); \
|
|
v2 = t; \
|
|
} while(0)
|
|
|
|
#define mm256_rol1x128_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 16 ); \
|
|
v2 = _mm256_alignr_epi8( v2, v1, 16 ); \
|
|
v1 = t; \
|
|
} while(0)
|
|
|
|
#define mm256_ror1x64_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 8 ); \
|
|
v1 = _mm256_alignr_epi8( v2, v1, 8 ); \
|
|
v2 = t; \
|
|
} while(0)
|
|
|
|
#define mm256_rol1x64_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 24 ); \
|
|
v2 = _mm256_alignr_epi8( v2, v1, 24 ); \
|
|
v1 = t; \
|
|
} while(0)
|
|
|
|
#define mm256_ror1x32_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 4 ); \
|
|
v1 = _mm256_alignr_epi8( v2, v1, 4 ); \
|
|
v2 = t; \
|
|
} while(0)
|
|
|
|
#define mm256_rol1x32_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 28 ); \
|
|
v2 = _mm256_alignr_epi8( v2, v1, 28 ); \
|
|
v1 = t; \
|
|
} while(0)
|
|
|
|
#define mm256_ror1x16_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 2 ); \
|
|
v1 = _mm256_alignr_epi8( v2, v1, 2 ); \
|
|
v2 = t; \
|
|
} while(0)
|
|
|
|
#define mm256_rol1x16_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 30 ); \
|
|
v2 = _mm256_alignr_epi8( v2, v1, 30 ); \
|
|
v1 = t; \
|
|
} while(0)
|
|
|
|
#define mm256_ror1x8_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 1 ); \
|
|
v1 = _mm256_alignr_epi8( v2, v1, 1 ); \
|
|
v2 = t; \
|
|
} while(0)
|
|
|
|
#define mm256_rol1x8_512( v1, v2 ) \
|
|
do { \
|
|
__m256i t = _mm256_alignr_epi8( v1, v2, 31 ); \
|
|
v2 = _mm256_alignr_epi8( v2, v1, 31 ); \
|
|
v1 = t; \
|
|
} while(0)
|
|
|
|
#endif // __AVX2__
|
|
#endif // __AVX__
|
|
#endif // SIMD_256_H__
|
|
|