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26 lines
1.4 KiB
C
26 lines
1.4 KiB
C
// Placeholder for now.
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//
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// This file will hold AArch64 SVE code, a replecement for NEON that uses vector length
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// agnostic instructions. This means the same code can be used on CPUs with different
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// SVE vector register lengths. This is not good for vectorized hashing.
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// Optimum hash is sensitive to the vector register length with different code
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// used for different register sizes. On X86_64 the vector length is tied to the CPU
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// feature making it simple and efficient to handle different lengths although it
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// results in multiple executables. Theoretically SVE could use a single executable for
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// any vector length.
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//
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// With the SVE vector length only known at run time it resultis in run time overhead
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// to test the vector length. Theoretically it could be tested at program loading and
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// appropriate libraries loaded. However I don't know if this can be done and if so
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// how to do it.
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//
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// SVE is not expected to be used for 128 bit vectors as it does not provide any
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// advantages over NEON. However, it may be implemented for testing purposes
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// because CPU with registers larger than 128 bits are currently very rare and very
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// expensive server class CPUs.
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//
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// N-way parallel hashing could be the best use of SVE, usimg the same code for all
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// vector lengths with the only variable being the number of lanes. This will still
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// require run time checking but should be lighter than substituting functions.
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