mirror of
https://github.com/JayDDee/cpuminer-opt.git
synced 2025-09-17 23:44:27 +00:00
571 lines
18 KiB
C
571 lines
18 KiB
C
#if !defined(SIMD_128_H__)
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#define SIMD_128_H__ 1
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#if defined(__SSE2__)
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///////////////////////////////////////////////////////////////////////////
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//
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// 128 bit SSE vectors
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//
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// SSE2 is required for 128 bit integer support. Some functions are also
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// optimized with SSSE3, SSE4.1 or AVX. Some of these more optimized
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// functions don't have SSE2 equivalents and their use would break SSE2
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// compatibility.
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//
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// Constants are an issue with simd. Simply put, immediate constants don't
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// exist. All simd constants either reside in memory or a register and
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// must be loaded from memory or generated at run time.
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//
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// Due to the cost of generating constants it is more efficient to
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// define a local const for repeated references to the same constant.
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//
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// One common use for simd constants is as a control index for vector
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// instructions like blend and shuffle. Alhough the ultimate instruction
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// may execute in a single clock cycle, generating the control index adds
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// several more cycles to the entire operation.
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//
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// All of the utilities here assume all data is in registers except
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// in rare cases where arguments are pointers.
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//
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// Some constants are generated using a memory overlay on the stack.
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//
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// Intrinsics automatically promote from REX to VEX when AVX is available
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// but ASM needs to be done manually.
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//
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///////////////////////////////////////////////////////////////////////////
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// Used instead if casting.
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typedef union
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{
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__m128i m128;
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uint32_t u32[4];
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} __attribute__ ((aligned (16))) m128_ovly;
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// Deprecated. AVX512 adds EVEX encoding (3rd operand) and other improvements
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// that make these functions either unnecessary or inefficient.
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// In cases where an explicit move betweeen GP & SIMD registers is still
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// necessary the cvt, set, or set1 intrinsics can be used allowing the
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// compiler to exploilt new features to produce optimum code.
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static inline __m128i mm128_mov64_128( const uint64_t n )
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{
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__m128i a;
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#if defined(__AVX__)
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asm( "vmovq %1, %0\n\t" : "=x"(a) : "r"(n) );
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#else
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asm( "movq %1, %0\n\t" : "=x"(a) : "r"(n) );
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#endif
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return a;
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}
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static inline __m128i mm128_mov32_128( const uint32_t n )
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{
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__m128i a;
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#if defined(__AVX__)
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asm( "vmovd %1, %0\n\t" : "=x"(a) : "r"(n) );
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#else
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asm( "movd %1, %0\n\t" : "=x"(a) : "r"(n) );
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#endif
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return a;
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}
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// Emulate broadcast & insert instructions not available in SSE2
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// FYI only, not used anywhere
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//#define mm128_bcast_m64( v ) _mm_shuffle_epi32( v, 0x44 )
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//#define mm128_bcast_m32( v ) _mm_shuffle_epi32( v, 0x00 )
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// Pseudo constants
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#define m128_zero _mm_setzero_si128()
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#define m128_one_128 mm128_mov64_128( 1 )
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//#define m128_one_64 _mm_set1_epi64x( 1 )
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#define m128_one_32 _mm_set1_epi32( 1 )
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// ASM avoids the need to initialize return variable to avoid compiler warning.
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// Macro abstracts function parentheses to look like an identifier.
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static inline __m128i mm128_neg1_fn()
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{
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__m128i a;
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#if defined(__AVX__)
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asm( "vpcmpeqq %0, %0, %0\n\t" : "=x"(a) );
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#else
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asm( "pcmpeqq %0, %0\n\t" : "=x"(a) );
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#endif
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return a;
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}
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#define m128_neg1 mm128_neg1_fn()
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#if defined(__SSE4_1__)
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/////////////////////////////
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//
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// _mm_insert_ps( _mm128i v1, __m128i v2, imm8 c )
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//
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// Fast and powerful but very limited in its application.
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// It requires SSE4.1 but only works with 128 bit vectors with 32 bit
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// elements. There is no equivalent instruction for 256 bit or 512 bit vectors.
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// There's no integer version. There's no 64 bit, 16 bit or byte element
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// sizing. It's unique.
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//
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// It can:
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// - zero any number of 32 bit elements of a 128 bit vector.
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// - extract any 32 bit element from one 128 bit vector and insert the
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// data to any 32 bit element of another 128 bit vector, or the same vector.
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// - do both simultaneoulsly.
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//
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// It can be used as a more efficient replacement for _mm_insert_epi32
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// or _mm_extract_epi32.
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//
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// Control byte definition:
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// c[3:0] zero mask
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// c[5:4] destination element selector
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// c[7:6] source element selector
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// Convert type and abbreviate name: eXtract Insert Mask = XIM
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#define mm128_xim_32( v1, v2, c ) \
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_mm_castps_si128( _mm_insert_ps( _mm_castsi128_ps( v1 ), \
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_mm_castsi128_ps( v2 ), c ) )
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/* Another way to do it with individual arguments.
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#define mm128_xim_32( v1, i1, v2, i2, mask ) \
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_mm_castps_si128( _mm_insert_ps( _mm_castsi128_ps( v1 ), \
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_mm_castsi128_ps( v2 ), \
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(mask) | ((i1)<<4) | ((i2)<<6) ) )
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*/
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// Examples of simple operations using xim:
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// Copy i to element c of dest and copy remaining elemnts from v.
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static inline __m128i mm128_insert_32( const __m128i v, const uint32_t i,
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const int c )
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{ return mm128_xim_32( v, mm128_mov32_128( i ), c<<4 ); }
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// Zero 32 bit elements when corresponding bit in 4 bit mask is set.
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static inline __m128i mm128_mask_32( const __m128i v, const int m )
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{ return mm128_xim_32( v, v, m ); }
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// Copy element i2 of v2 to element i1 of dest and copy remaining elements from v1.
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#define mm128_mov32_32( v1, i1, v2, i2 ) \
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mm128_xim_32( v1, v2, ( (i1)<<4 ) | ( (i2)<<6 ) )
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#endif // SSE4_1
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//
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// Basic operations without equivalent SIMD intrinsic
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// Bitwise not (~v)
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#if defined(__AVX512VL__)
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//TODO Enable for AVX10_256
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static inline __m128i mm128_not( const __m128i v )
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{ return _mm_ternarylogic_epi64( v, v, v, 1 ); }
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#else
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#define mm128_not( v ) _mm_xor_si128( v, m128_neg1 )
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#endif
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// Add 4 values, fewer dependencies than sequential addition.
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#define mm128_add4_64( a, b, c, d ) \
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_mm_add_epi64( _mm_add_epi64( a, b ), _mm_add_epi64( c, d ) )
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#define mm128_add4_32( a, b, c, d ) \
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_mm_add_epi32( _mm_add_epi32( a, b ), _mm_add_epi32( c, d ) )
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#define mm128_add4_16( a, b, c, d ) \
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_mm_add_epi16( _mm_add_epi16( a, b ), _mm_add_epi16( c, d ) )
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#define mm128_add4_8( a, b, c, d ) \
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_mm_add_epi8( _mm_add_epi8( a, b ), _mm_add_epi8( c, d ) )
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#define mm128_xor4( a, b, c, d ) \
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_mm_xor_si128( _mm_xor_si128( a, b ), _mm_xor_si128( c, d ) )
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//
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// Vector pointer cast
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// p = any aligned pointer
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// returns p as pointer to vector type
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#define castp_m128i(p) ((__m128i*)(p))
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// p = any aligned pointer
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// returns *p, watch your pointer arithmetic
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#define cast_m128i(p) (*((__m128i*)(p)))
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// p = any aligned pointer, i = scaled array index
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// returns value p[i]
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#define casti_m128i(p,i) (((__m128i*)(p))[(i)])
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// p = any aligned pointer, o = scaled offset
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// returns pointer p+o
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#define casto_m128i(p,o) (((__m128i*)(p))+(o))
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// Memory functions
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// Mostly for convenience, avoids calculating bytes.
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// Assumes data is alinged and integral.
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// n = number of __m128i, bytes/16
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static inline void memset_zero_128( __m128i *dst, const int n )
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{ for ( int i = 0; i < n; i++ ) dst[i] = m128_zero; }
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static inline void memset_128( __m128i *dst, const __m128i a, const int n )
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{ for ( int i = 0; i < n; i++ ) dst[i] = a; }
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static inline void memcpy_128( __m128i *dst, const __m128i *src, const int n )
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{ for ( int i = 0; i < n; i ++ ) dst[i] = src[i]; }
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#if defined(__AVX512VL__)
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//TODO Enable for AVX10_256
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// a ^ b ^ c
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#define mm128_xor3( a, b, c ) _mm_ternarylogic_epi64( a, b, c, 0x96 )
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// a & b & c
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#define mm128_and3( a, b, c ) _mm_ternarylogic_epi64( a, b, c, 0x80 )
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// a | b | c
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#define mm128_or3( a, b, c ) _mm_ternarylogic_epi64( a, b, c, 0xfe )
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// a ^ ( b & c )
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#define mm128_xorand( a, b, c ) _mm_ternarylogic_epi64( a, b, c, 0x78 )
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// a & ( b ^ c )
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#define mm128_andxor( a, b, c ) _mm_ternarylogic_epi64( a, b, c, 0x60 )
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// a ^ ( b | c )
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#define mm128_xoror( a, b, c ) _mm_ternarylogic_epi64( a, b, c, 0x1e )
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// a ^ ( ~b & c )
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#define mm128_xorandnot( a, b, c ) _mm_ternarylogic_epi64( a, b, c, 0xd2 )
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// a | ( b & c )
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#define mm128_orand( a, b, c ) _mm_ternarylogic_epi64( a, b, c, 0xf8 )
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// ~( a ^ b ), same as (~a) ^ b
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#define mm128_xnor( a, b ) _mm_ternarylogic_epi64( a, b, b, 0x81 )
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#else
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#define mm128_xor3( a, b, c ) _mm_xor_si128( a, _mm_xor_si128( b, c ) )
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#define mm128_and3( a, b, c ) _mm_and_si128( a, _mm_and_si128( b, c ) )
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#define mm128_or3( a, b, c ) _mm_or_si128( a, _mm_or_si128( b, c ) )
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#define mm128_xorand( a, b, c ) _mm_xor_si128( a, _mm_and_si128( b, c ) )
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#define mm128_andxor( a, b, c ) _mm_and_si128( a, _mm_xor_si128( b, c ))
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#define mm128_xoror( a, b, c ) _mm_xor_si128( a, _mm_or_si128( b, c ) )
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#define mm128_xorandnot( a, b, c ) _mm_xor_si128( a, _mm_andnot_si128( b, c ) )
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#define mm128_orand( a, b, c ) _mm_or_si128( a, _mm_and_si128( b, c ) )
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#define mm128_xnor( a, b ) mm128_not( _mm_xor_si128( a, b ) )
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#endif
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// Mask making
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// Equivalent of AVX512 _mm_movepi64_mask & _mm_movepi32_mask.
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// Returns 2 or 4 bit integer mask from MSBit of 64 or 32 bit elements.
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// Effectively a sign test.
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#define mm_movmask_64( v ) \
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_mm_castpd_si128( _mm_movmask_pd( _mm_castsi128_pd( v ) ) )
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#define mm_movmask_32( v ) \
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_mm_castps_si128( _mm_movmask_ps( _mm_castsi128_ps( v ) ) )
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//
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// Bit rotations
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// x2 rotates elements in 2 individual vectors in a double buffered
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// optimization for SSE2, does nothing for AVX512 but is there for
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// transparency.
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#if defined(__AVX512VL__)
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//TODO Enable for AVX10_256
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#define mm128_ror_64 _mm_ror_epi64
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#define mm128_rol_64 _mm_rol_epi64
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#define mm128_ror_32 _mm_ror_epi32
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#define mm128_rol_32 _mm_rol_epi32
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#define mm128_rorx2_64( v1, v0, c ) \
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_mm_ror_epi64( v0, c ); \
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_mm_ror_epi64( v1, c )
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#define mm128_rolx2_64( v1, v0, c ) \
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_mm_rol_epi64( v0, c ); \
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_mm_rol_epi64( v1, c )
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#define mm128_rorx2_32( v1, v0, c ) \
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_mm_ror_epi32( v0, c ); \
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_mm_ror_epi32( v1, c )
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#define mm128_rolx2_32( v1, v0, c ) \
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_mm_rol_epi32( v0, c ); \
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_mm_rol_epi32( v1, c )
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#else // SSE2
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#define mm128_ror_64( v, c ) \
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_mm_or_si128( _mm_srli_epi64( v, c ), _mm_slli_epi64( v, 64-(c) ) )
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#define mm128_rol_64( v, c ) \
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_mm_or_si128( _mm_slli_epi64( v, c ), _mm_srli_epi64( v, 64-(c) ) )
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#define mm128_ror_32( v, c ) \
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_mm_or_si128( _mm_srli_epi32( v, c ), _mm_slli_epi32( v, 32-(c) ) )
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#define mm128_rol_32( v, c ) \
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_mm_or_si128( _mm_slli_epi32( v, c ), _mm_srli_epi32( v, 32-(c) ) )
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#define mm128_rorx2_64( v1, v0, c ) \
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{ \
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__m128i t0 = _mm_srli_epi64( v0, c ); \
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__m128i t1 = _mm_srli_epi64( v1, c ); \
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v0 = _mm_slli_epi64( v0, 64-(c) ); \
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v1 = _mm_slli_epi64( v1, 64-(c) ); \
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v0 = _mm_or_si256( v0, t0 ); \
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v1 = _mm_or_si256( v1, t1 ); \
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}
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#define mm128_rolx2_64( v1, v0, c ) \
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{ \
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__m128i t0 = _mm_slli_epi64( v0, c ); \
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__m128i t1 = _mm_slli_epi64( v1, c ); \
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v0 = _mm_srli_epi64( v0, 64-(c) ); \
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v1 = _mm_srli_epi64( v1, 64-(c) ); \
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v0 = _mm_or_si256( v0, t0 ); \
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v1 = _mm_or_si256( v1, t1 ); \
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}
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#define mm128_rorx2_32( v1, v0, c ) \
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{ \
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__m128i t0 = _mm_srli_epi32( v0, c ); \
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__m128i t1 = _mm_srli_epi32( v1, c ); \
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v0 = _mm_slli_epi32( v0, 32-(c) ); \
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v1 = _mm_slli_epi32( v1, 32-(c) ); \
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v0 = _mm_or_si256( v0, t0 ); \
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v1 = _mm_or_si256( v1, t1 ); \
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}
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#define mm128_rolx2_32( v1, v0, c ) \
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{ \
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__m128i t0 = _mm_slli_epi32( v0, c ); \
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__m128i t1 = _mm_slli_epi32( v1, c ); \
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v0 = _mm_srli_epi32( v0, 32-(c) ); \
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v1 = _mm_srli_epi32( v1, 32-(c) ); \
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v0 = _mm_or_si256( v0, t0 ); \
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v1 = _mm_or_si256( v1, t1 ); \
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}
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#endif // AVX512 else SSE2
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// Cross lane shuffles
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//
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// Limited 2 input shuffle, combines shuffle with blend. The destination low
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// half is always taken from v1, and the high half from v2.
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#define mm128_shuffle2_64( v1, v2, c ) \
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_mm_castpd_si128( _mm_shuffle_pd( _mm_castsi128_pd( v1 ), \
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_mm_castsi128_pd( v2 ), c ) );
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#define mm128_shuffle2_32( v1, v2, c ) \
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_mm_castps_si128( _mm_shuffle_ps( _mm_castsi128_ps( v1 ), \
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_mm_castsi128_ps( v2 ), c ) );
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// Rotate vector elements accross all lanes
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#define mm128_swap_64( v ) _mm_shuffle_epi32( v, 0x4e )
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#define mm128_shuflr_64 mm128_swap_64
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#define mm128_shufll_64 mm128_swap_64
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#define mm128_shuflr_32( v ) _mm_shuffle_epi32( v, 0x39 )
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#define mm128_shufll_32( v ) _mm_shuffle_epi32( v, 0x93 )
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/* Not used
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#if defined(__SSSE3__)
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// Rotate right by c bytes, no SSE2 equivalent.
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static inline __m128i mm128_shuflr_x8( const __m128i v, const int c )
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{ return _mm_alignr_epi8( v, v, c ); }
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#endif
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*/
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// Rotate 64 bit lanes
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#define mm128_swap64_32( v ) _mm_shuffle_epi32( v, 0xb1 )
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#define mm128_shuflr64_32 mm128_swap64_32
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#define mm128_shufll64_32 mm128_swap64_32
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//TODO Enable for AVX10_256
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#if defined(__AVX512VL__)
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#define m1286_shuflr64_24( v ) _mm_ror_epi64( v, 24 )
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#elif defined(__SSSE3__)
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#define mm128_shuflr64_24( v ) \
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_mm_shuffle_epi8( v, _mm_set_epi64x( \
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0x0a09080f0e0d0c0b, 0x0201000706050403 ) )
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#else
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#define mm128_shuflr64_24( v ) mm128_ror_64( v, 24 )
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#endif
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#if defined(__AVX512VL__)
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#define mm128_shuflr64_16( v ) _mm_ror_epi64( v, 16 )
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#elif defined(__SSSE3__)
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#define mm128_shuflr64_16( v ) \
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_mm_shuffle_epi8( v, _mm_set_epi64x( \
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0x09080f0e0d0c0b0a, 0x0100070605040302 ) )
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#else
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#define mm128_shuflr64_16( v ) mm128_ror_64( v, 16 )
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#endif
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// Rotate 32 bit lanes
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#if defined(__AVX512VL__)
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#define mm128_swap32_16( v ) _mm_ror_epi32( v, 16 )
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#elif defined(__SSSE3__)
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#define mm128_swap32_16( v ) \
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_mm_shuffle_epi8( v, _mm_set_epi64x( \
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|
0x0d0c0f0e09080b0a, 0x0504070601000302 ) )
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#else
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#define mm128_swap32_16( v ) mm128_ror_32( v, 16 )
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#endif
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#define mm128_shuflr32_16 mm128_swap32_16
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#define mm128_shufll32_16 mm128_swap32_16
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|
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#if defined(__AVX512VL__)
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#define mm128_shuflr32_8( v ) _mm_ror_epi32( v, 8 )
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#elif defined(__SSSE3__)
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#define mm128_shuflr32_8( v ) \
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_mm_shuffle_epi8( v, _mm_set_epi64x( \
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|
0x0c0f0e0d080b0a09, 0x0407060500030201 ) )
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#else
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#define mm128_shuflr32_8( v ) mm128_ror_32( v, 8 )
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#endif
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//
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// Endian byte swap.
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|
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#if defined(__SSSE3__)
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|
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#define mm128_bswap_128( v ) \
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_mm_shuffle_epi8( v, _mm_set_epi64x( 0x0001020304050607, \
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|
0x08090a0b0c0d0e0f ) )
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|
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#define mm128_bswap_64( v ) \
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_mm_shuffle_epi8( v, _mm_set_epi64x( 0x08090a0b0c0d0e0f, \
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|
0x0001020304050607 ) )
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|
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|
#define mm128_bswap_32( v ) \
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_mm_shuffle_epi8( v, _mm_set_epi64x( 0x0c0d0e0f08090a0b, \
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|
0x0405060700010203 ) )
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|
|
|
#define mm128_bswap_16( v ) \
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|
_mm_shuffle_epi8( v, _mm_set_epi64x( 0x0e0f0c0d0a0b0809, \
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|
0x0607040502030001 )
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|
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// 8 byte qword * 8 qwords * 2 lanes = 128 bytes
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|
#define mm128_block_bswap_64( d, s ) do \
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|
{ \
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|
__m128i ctl = _mm_set_epi64x( 0x08090a0b0c0d0e0f, 0x0001020304050607 ); \
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|
casti_m128i( d, 0 ) = _mm_shuffle_epi8( casti_m128i( s, 0 ), ctl ); \
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|
casti_m128i( d, 1 ) = _mm_shuffle_epi8( casti_m128i( s, 1 ), ctl ); \
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|
casti_m128i( d, 2 ) = _mm_shuffle_epi8( casti_m128i( s, 2 ), ctl ); \
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|
casti_m128i( d, 3 ) = _mm_shuffle_epi8( casti_m128i( s, 3 ), ctl ); \
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|
casti_m128i( d, 4 ) = _mm_shuffle_epi8( casti_m128i( s, 4 ), ctl ); \
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|
casti_m128i( d, 5 ) = _mm_shuffle_epi8( casti_m128i( s, 5 ), ctl ); \
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|
casti_m128i( d, 6 ) = _mm_shuffle_epi8( casti_m128i( s, 6 ), ctl ); \
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|
casti_m128i( d, 7 ) = _mm_shuffle_epi8( casti_m128i( s, 7 ), ctl ); \
|
|
} while(0)
|
|
|
|
// 4 byte dword * 8 dwords * 4 lanes = 128 bytes
|
|
#define mm128_block_bswap_32( d, s ) do \
|
|
{ \
|
|
__m128i ctl = _mm_set_epi64x( 0x0c0d0e0f08090a0b, 0x0405060700010203 ); \
|
|
casti_m128i( d, 0 ) = _mm_shuffle_epi8( casti_m128i( s, 0 ), ctl ); \
|
|
casti_m128i( d, 1 ) = _mm_shuffle_epi8( casti_m128i( s, 1 ), ctl ); \
|
|
casti_m128i( d, 2 ) = _mm_shuffle_epi8( casti_m128i( s, 2 ), ctl ); \
|
|
casti_m128i( d, 3 ) = _mm_shuffle_epi8( casti_m128i( s, 3 ), ctl ); \
|
|
casti_m128i( d, 4 ) = _mm_shuffle_epi8( casti_m128i( s, 4 ), ctl ); \
|
|
casti_m128i( d, 5 ) = _mm_shuffle_epi8( casti_m128i( s, 5 ), ctl ); \
|
|
casti_m128i( d, 6 ) = _mm_shuffle_epi8( casti_m128i( s, 6 ), ctl ); \
|
|
casti_m128i( d, 7 ) = _mm_shuffle_epi8( casti_m128i( s, 7 ), ctl ); \
|
|
} while(0)
|
|
|
|
#else // SSE2
|
|
|
|
static inline __m128i mm128_bswap_64( __m128i v )
|
|
{
|
|
v = _mm_or_si128( _mm_slli_epi16( v, 8 ), _mm_srli_epi16( v, 8 ) );
|
|
v = _mm_shufflelo_epi16( v, _MM_SHUFFLE( 0, 1, 2, 3 ) );
|
|
return _mm_shufflehi_epi16( v, _MM_SHUFFLE( 0, 1, 2, 3 ) );
|
|
}
|
|
|
|
static inline __m128i mm128_bswap_32( __m128i v )
|
|
{
|
|
v = _mm_or_si128( _mm_slli_epi16( v, 8 ), _mm_srli_epi16( v, 8 ) );
|
|
v = _mm_shufflelo_epi16( v, _MM_SHUFFLE( 2, 3, 0, 1 ) );
|
|
return _mm_shufflehi_epi16( v, _MM_SHUFFLE( 2, 3, 0, 1 ) );
|
|
}
|
|
|
|
static inline __m128i mm128_bswap_16( __m128i v )
|
|
{
|
|
return _mm_or_si128( _mm_slli_epi16( v, 8 ), _mm_srli_epi16( v, 8 ) );
|
|
}
|
|
|
|
#define mm128_bswap_128( v ) \
|
|
mm128_swap_64( mm128_bswap_64( v ) )
|
|
|
|
static inline void mm128_block_bswap_64( __m128i *d, const __m128i *s )
|
|
{
|
|
d[0] = mm128_bswap_64( s[0] );
|
|
d[1] = mm128_bswap_64( s[1] );
|
|
d[2] = mm128_bswap_64( s[2] );
|
|
d[3] = mm128_bswap_64( s[3] );
|
|
d[4] = mm128_bswap_64( s[4] );
|
|
d[5] = mm128_bswap_64( s[5] );
|
|
d[6] = mm128_bswap_64( s[6] );
|
|
d[7] = mm128_bswap_64( s[7] );
|
|
}
|
|
|
|
static inline void mm128_block_bswap_32( __m128i *d, const __m128i *s )
|
|
{
|
|
d[0] = mm128_bswap_32( s[0] );
|
|
d[1] = mm128_bswap_32( s[1] );
|
|
d[2] = mm128_bswap_32( s[2] );
|
|
d[3] = mm128_bswap_32( s[3] );
|
|
d[4] = mm128_bswap_32( s[4] );
|
|
d[5] = mm128_bswap_32( s[5] );
|
|
d[6] = mm128_bswap_32( s[6] );
|
|
d[7] = mm128_bswap_32( s[7] );
|
|
}
|
|
|
|
#endif // SSSE3 else SSE2
|
|
|
|
// alignr instruction for 32 & 64 bit elements is only available with AVX512
|
|
// but emulated here. Behaviour is consistent with Intel alignr intrinsics.
|
|
|
|
#if defined(__SSSE3__)
|
|
|
|
#define mm128_alignr_64( hi, lo, c ) _mm_alignr_epi8( hi, lo, (c)*8 )
|
|
#define mm128_alignr_32( hi, lo, c ) _mm_alignr_epi8( hi, lo, (c)*4 )
|
|
|
|
#else
|
|
|
|
#define mm128_alignr_64( hi, lo, c ) \
|
|
_mm_or_si128( _mm_slli_si128( hi, (c)*8 ), _mm_srli_si128( lo, (c)*8 ) )
|
|
|
|
#define mm128_alignr_32( hi, lo, c ) \
|
|
_mm_or_si128( _mm_slli_si128( lo, (c)*4 ), _mm_srli_si128( hi, (c)*4 ) )
|
|
|
|
#endif
|
|
|
|
#endif // __SSE2__
|
|
#endif // SIMD_128_H__
|