mirror of
https://github.com/JayDDee/cpuminer-opt.git
synced 2025-09-17 23:44:27 +00:00
630 lines
14 KiB
C
630 lines
14 KiB
C
#if !defined(SYSINFOS_C__)
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#define SYSINFOS_C__
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/**
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* Unit to read cpu informations
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*
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* tpruvot 2014
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* JayDDee 2019
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*
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*/
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#include <stdio.h>
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#include <ctype.h>
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#include <stdlib.h>
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#include <string.h>
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#include "miner.h"
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#ifndef WIN32
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// 1035g1: /sys/devices/platform/coretemp.0/hwmon/hwmon3/temp1_input
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// 1035g1: /sys/class/hwmon/hwmon1/temp1_input wrong temp
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// ryzen has no /sys/devices/platform/coretemp.0
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// ryzen: /sys/class/hwmon/hwmon0
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// 2400: /sys/class/hwmon/hwmon0/temp1_input incorrect temp
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// 2400 has no /sys/class/hwmon/hwmon2/temp1_input
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// 2400 /sys/devices/platform/coretemp.0/hwmon/hwmon1/temp1_input ok
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// 6700 /sys/devices/platform/coretemp.0/hwmon/hwmon2/temp1_input
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// 6700 /sys/class/hwmon/hwmon2/temp1_input
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// /sys/devices/platform/coretemp.0/hwmon/hwmon0/temp2_input never exists
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// /sys/class/hwmon/hwmon0/temp2_input doesn't exist or shows wrong temp (sys16)
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// /sys/class/hwmon/hwmon0/device/temp1_input doesn't exist
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// the first 3 will find i5-2400, i7-6700k, r7-1700, i5-1035g1.
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// The others are left in for legacy, some should probably be removed.
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#define HWMON_PATH1 \
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"/sys/devices/platform/coretemp.0/hwmon/hwmon3/temp1_input"
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#define HWMON_PATH2 \
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"/sys/devices/platform/coretemp.0/hwmon/hwmon1/temp1_input"
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#define HWMON_PATH3 \
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"/sys/devices/platform/coretemp.0/hwmon/hwmon2/temp1_input"
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#define HWMON_PATH \
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"/sys/class/hwmon/hwmon2/temp1_input"
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// need this for Ryzen
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#define HWMON_ALT \
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"/sys/class/hwmon/hwmon0/temp1_input"
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/*
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#define HWMON_ALT1 \
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"/sys/devices/platform/coretemp.0/hwmon/hwmon1/temp1_input"
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*/
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// This shows wrong temp on i5-1035g1
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#define HWMON_ALT2 \
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"/sys/class/hwmon/hwmon1/temp1_input"
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// None of these work on any of the cpus above.
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#define HWMON_ALT3 \
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"/sys/devices/platform/coretemp.0/hwmon/hwmon0/temp2_input"
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#define HWMON_ALT4 \
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"/sys/class/hwmon/hwmon0/temp2_input"
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#define HWMON_ALT5 \
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"/sys/class/hwmon/hwmon0/device/temp1_input"
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static inline float linux_cputemp(int core)
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{
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float tc = 0.0;
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FILE *fd;
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uint32_t val = 0;
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fd = fopen(HWMON_PATH1, "r");
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if (!fd)
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fd = fopen(HWMON_PATH2, "r");
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if (!fd)
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fd = fopen(HWMON_PATH3, "r");
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if (!fd)
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fd = fopen(HWMON_PATH, "r");
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if (!fd)
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fd = fopen(HWMON_ALT, "r");
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if (!fd)
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return tc;
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if ( fscanf( fd, "%d", &val ) )
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tc = val / 1000.0;
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fclose( fd );
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return tc;
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}
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#define CPUFREQ_PATH0\
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"/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq"
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#define CPUFREQ_PATHn \
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"/sys/devices/system/cpu/cpu%d/cpufreq/scaling_cur_freq"
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static inline float linux_cpufreq(int core)
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{
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FILE *fd = fopen( CPUFREQ_PATH0, "r" );
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long int freq = 0;
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if ( !fd ) return (float)freq;
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if ( !fscanf( fd, "%ld", &freq ) ) freq = 0;
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fclose( fd );
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return (float)freq;
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}
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static inline void linux_cpu_hilo_freq( float *lo, float *hi )
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{
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long int freq = 0, hi_freq = 0, lo_freq = 0x7fffffff;
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for ( int i = 0; i < num_cpus; i++ )
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{
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char path[64];
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sprintf( path, CPUFREQ_PATHn, i );
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FILE *fd = fopen( path, "r" );
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if ( !fd ) return;
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else if ( fscanf( fd, "%ld", &freq ) )
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{
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if ( freq > hi_freq ) hi_freq = freq;
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if ( freq < lo_freq ) lo_freq = freq;
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}
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fclose( fd );
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}
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*hi = (float)hi_freq;
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*lo = (float)lo_freq;
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}
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#else /* WIN32 */
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static inline float win32_cputemp( int core )
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{
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// todo
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return 0.0;
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}
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#endif /* !WIN32 */
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/* exports */
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static inline float cpu_temp( int core )
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{
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#ifdef WIN32
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return win32_cputemp( core );
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#else
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return linux_cputemp( core );
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#endif
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}
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static inline uint32_t cpu_clock( int core )
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{
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#ifdef WIN32
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return 0;
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#else
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return linux_cpufreq( core );
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#endif
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}
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static inline int cpu_fanpercent()
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{
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return 0;
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}
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#ifndef __arm__
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static inline void cpuid(int functionnumber, int output[4]) {
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#if defined (_MSC_VER) || defined (__INTEL_COMPILER)
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// Microsoft or Intel compiler, intrin.h included
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__cpuidex(output, functionnumber, 0);
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#elif defined(__GNUC__) || defined(__clang__)
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// use inline assembly, Gnu/AT&T syntax
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int a, b, c, d;
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asm volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(functionnumber), "c"(0));
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output[0] = a;
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output[1] = b;
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output[2] = c;
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output[3] = d;
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#else
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// unknown platform. try inline assembly with masm/intel syntax
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__asm {
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mov eax, functionnumber
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xor ecx, ecx
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cpuid;
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mov esi, output
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mov[esi], eax
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mov[esi + 4], ebx
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mov[esi + 8], ecx
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mov[esi + 12], edx
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}
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#endif
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}
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#else /* !__arm__ */
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#define cpuid(fn, out) out[0] = 0;
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#endif
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static inline void cpu_getname(char *outbuf, size_t maxsz)
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{
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memset(outbuf, 0, maxsz);
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#ifdef WIN32
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char brand[0xC0] = { 0 };
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int output[4] = { 0 }, ext;
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cpuid(0x80000000, output);
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ext = output[0];
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if (ext >= 0x80000004)
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{
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for (int i = 2; i <= (ext & 0xF); i++)
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{
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cpuid(0x80000000+i, output);
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memcpy(&brand[(i-2) * 4*sizeof(int)], output, 4*sizeof(int));
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}
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snprintf(outbuf, maxsz, "%s", brand);
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}
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else
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{
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// Fallback, for the i7-5775C will output
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// Intel64 Family 6 Model 71 Stepping 1, GenuineIntel
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snprintf(outbuf, maxsz, "%s", getenv("PROCESSOR_IDENTIFIER"));
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}
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#else
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// Intel(R) Xeon(R) CPU E3-1245 V2 @ 3.40GHz
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FILE *fd = fopen("/proc/cpuinfo", "rb");
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char *buf = NULL, *p, *eol;
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size_t size = 0;
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if (!fd) return;
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while(getdelim(&buf, &size, 0, fd) != -1)
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{
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if (buf && (p = strstr(buf, "model name\t")) && strstr(p, ":"))
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{
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p = strstr(p, ":");
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if (p)
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{
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p += 2;
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eol = strstr(p, "\n"); if (eol) *eol = '\0';
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snprintf(outbuf, maxsz, "%s", p);
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}
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break;
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}
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}
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free(buf);
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fclose(fd);
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#endif
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}
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static inline void cpu_getmodelid(char *outbuf, size_t maxsz)
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{
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memset(outbuf, 0, maxsz);
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#ifdef WIN32
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// For the i7-5775C will output 6:4701:8
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snprintf(outbuf, maxsz, "%s:%s:%s", getenv("PROCESSOR_LEVEL"), // hexa ?
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getenv("PROCESSOR_REVISION"), getenv("NUMBER_OF_PROCESSORS"));
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#else
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FILE *fd = fopen("/proc/cpuinfo", "rb");
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char *buf = NULL, *p;
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int cpufam = 0, model = 0, stepping = 0;
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size_t size = 0;
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if (!fd) return;
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while(getdelim(&buf, &size, 0, fd) != -1)
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{
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if (buf && (p = strstr(buf, "cpu family\t")) && strstr(p, ":"))
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{
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p = strstr(p, ":");
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if (p)
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{
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p += 2;
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cpufam = atoi(p);
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}
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}
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if (buf && (p = strstr(buf, "model\t")) && strstr(p, ":"))
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{
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p = strstr(p, ":");
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if (p)
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{
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p += 2;
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model = atoi(p);
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}
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}
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if (buf && (p = strstr(buf, "stepping\t")) && strstr(p, ":"))
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{
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p = strstr(p, ":");
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if (p)
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{
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p += 2;
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stepping = atoi(p);
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}
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}
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if (cpufam && model && stepping)
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{
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snprintf( outbuf, maxsz, "%x:%02x%02x:%d", cpufam, model, stepping,
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num_cpus);
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outbuf[maxsz-1] = '\0';
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break;
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}
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}
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free(buf);
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fclose(fd);
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#endif
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}
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// http://en.wikipedia.org/wiki/CPUID
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// CPUID commands
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#define VENDOR_ID (0)
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#define CPU_INFO (1)
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#define CACHE_TLB_DESCRIPTOR (2)
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#define EXTENDED_FEATURES (7)
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#define HIGHEST_EXT_FUNCTION (0x80000000)
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#define EXTENDED_CPU_INFO (0x80000001)
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#define CPU_BRAND_1 (0x80000002)
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#define CPU_BRAND_2 (0x80000003)
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#define CPU_BRAND_3 (0x80000004)
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// Registers
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#define EAX_Reg (0)
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#define EBX_Reg (1)
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#define ECX_Reg (2)
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#define EDX_Reg (3)
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// Feature flags
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// CPU_INFO ECX
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#define SSE3_Flag 1
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#define SSSE3_Flag (1<< 9)
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#define XOP_Flag (1<<11)
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#define FMA3_Flag (1<<12)
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#define AES_Flag (1<<25)
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#define SSE41_Flag (1<<19)
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#define SSE42_Flag (1<<20)
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#define AES_Flag (1<<25)
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#define XSAVE_Flag (1<<26)
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#define OSXSAVE_Flag (1<<27)
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#define AVX_Flag (1<<28)
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// CPU_INFO EDX
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#define SSE_Flag (1<<25)
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#define SSE2_Flag (1<<26)
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// EXTENDED_FEATURES EBX
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#define AVX2_Flag (1<< 5)
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#define AVX512F_Flag (1<<16)
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#define AVX512DQ_Flag (1<<17)
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#define SHA_Flag (1<<29)
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#define AVX512BW_Flag (1<<30)
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#define AVX512VL_Flag (1<<31)
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// EXTENDED_FEATURES ECX
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#define AVX512VBMI_Flag (1<<1)
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#define AVX512VBMI2_Flag (1<<6)
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#define VAES_Flag (1<<9)
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// Use this to detect presence of feature
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#define AVX_mask (AVX_Flag|XSAVE_Flag|OSXSAVE_Flag)
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#define FMA3_mask (FMA3_Flag|AVX_mask)
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#define AVX512_mask (AVX512VL_Flag|AVX512BW_Flag|AVX512DQ_Flag|AVX512F_Flag)
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static inline bool has_sha()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( EXTENDED_FEATURES, cpu_info );
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return cpu_info[ EBX_Reg ] & SHA_Flag;
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#endif
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}
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static inline bool has_sse2()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( CPU_INFO, cpu_info );
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return cpu_info[ EDX_Reg ] & SSE2_Flag;
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#endif
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}
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// nehalem and above, no AVX on nehalem
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static inline bool has_aes_ni()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( CPU_INFO, cpu_info );
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return cpu_info[ ECX_Reg ] & AES_Flag;
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#endif
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}
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// westmere and above
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static inline bool has_avx()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( CPU_INFO, cpu_info );
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return ( ( cpu_info[ ECX_Reg ] & AVX_mask ) == AVX_mask );
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#endif
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}
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// haswell and above
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static inline bool has_avx2()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( EXTENDED_FEATURES, cpu_info );
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return cpu_info[ EBX_Reg ] & AVX2_Flag;
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#endif
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}
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static inline bool has_avx512f()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( EXTENDED_FEATURES, cpu_info );
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return cpu_info[ EBX_Reg ] & AVX512F_Flag;
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#endif
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}
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static inline bool has_avx512dq()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( EXTENDED_FEATURES, cpu_info );
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return cpu_info[ EBX_Reg ] & AVX512DQ_Flag;
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#endif
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}
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static inline bool has_avx512bw()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( EXTENDED_FEATURES, cpu_info );
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return cpu_info[ EBX_Reg ] & AVX512BW_Flag;
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#endif
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}
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static inline bool has_avx512vl()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( EXTENDED_FEATURES, cpu_info );
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return cpu_info[ EBX_Reg ] & AVX512VL_Flag;
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#endif
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}
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// Minimum to be useful
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static inline bool has_avx512()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( EXTENDED_FEATURES, cpu_info );
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return ( ( cpu_info[ EBX_Reg ] & AVX512_mask ) == AVX512_mask );
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#endif
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}
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// AMD Zen3 added support for 256 bit VAES without requiring AVX512.
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// The original Intel spec requires AVX512F to support 512 bit VAES and
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// requires AVX512VL to support 256 bit VAES.
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// The CPUID VAES bit alone can't distiguish 256 vs 512 bit.
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// If necessary:
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// VAES 256 & 512 = VAES && AVX512VL
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// VAES 512 = VAES && AVX512F
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// VAES 256 = ( VAES && AVX512VL ) || ( VAES && !AVX512F )
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// VAES 512 only = VAES && AVX512F && !AVX512VL
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// VAES 256 only = VAES && !AVX512F
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static inline bool has_vaes()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( EXTENDED_FEATURES, cpu_info );
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return cpu_info[ ECX_Reg ] & VAES_Flag;
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#endif
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}
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// AMD only
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static inline bool has_xop()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( EXTENDED_CPU_INFO, cpu_info );
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return cpu_info[ ECX_Reg ] & XOP_Flag;
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#endif
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}
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static inline bool has_fma3()
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{
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#ifdef __arm__
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return false;
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#else
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int cpu_info[4] = { 0 };
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cpuid( CPU_INFO, cpu_info );
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return ( ( cpu_info[ ECX_Reg ] & FMA3_mask ) == FMA3_mask );
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#endif
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}
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static inline bool has_sse42()
|
|
{
|
|
#ifdef __arm__
|
|
return false;
|
|
#else
|
|
int cpu_info[4] = { 0 };
|
|
cpuid( CPU_INFO, cpu_info );
|
|
return cpu_info[ ECX_Reg ] & SSE42_Flag;
|
|
#endif
|
|
}
|
|
|
|
static inline bool has_sse()
|
|
{
|
|
#ifdef __arm__
|
|
return false;
|
|
#else
|
|
int cpu_info[4] = { 0 };
|
|
cpuid( CPU_INFO, cpu_info );
|
|
return cpu_info[ EDX_Reg ] & SSE_Flag;
|
|
#endif
|
|
}
|
|
|
|
static inline uint32_t cpuid_get_highest_function_number()
|
|
{
|
|
uint32_t cpu_info[4] = {0};
|
|
cpuid( VENDOR_ID, cpu_info);
|
|
return cpu_info[ EAX_Reg ];
|
|
}
|
|
|
|
static inline void cpuid_get_highest_function( char* s )
|
|
{
|
|
uint32_t fn = cpuid_get_highest_function_number();
|
|
switch (fn)
|
|
{
|
|
case 0x16:
|
|
strcpy( s, "Skylake" );
|
|
break;
|
|
case 0xd:
|
|
strcpy( s, "IvyBridge" );
|
|
break;
|
|
case 0xb:
|
|
strcpy( s, "Corei7" );
|
|
break;
|
|
case 0xa:
|
|
strcpy( s, "Core2" );
|
|
break;
|
|
default:
|
|
sprintf( s, "undefined %x", fn );
|
|
}
|
|
}
|
|
|
|
static inline void cpu_bestfeature(char *outbuf, size_t maxsz)
|
|
{
|
|
#ifdef __arm__
|
|
sprintf(outbuf, "ARM");
|
|
#else
|
|
int cpu_info[4] = { 0 };
|
|
int cpu_info_adv[4] = { 0 };
|
|
cpuid( CPU_INFO, cpu_info );
|
|
cpuid( EXTENDED_FEATURES, cpu_info_adv );
|
|
|
|
if ( has_avx() && has_avx2() )
|
|
sprintf(outbuf, "AVX2");
|
|
else if ( has_avx() )
|
|
sprintf(outbuf, "AVX");
|
|
else if ( has_fma3() )
|
|
sprintf(outbuf, "FMA3");
|
|
else if ( has_xop() )
|
|
sprintf(outbuf, "XOP");
|
|
else if ( has_sse42() )
|
|
sprintf(outbuf, "SSE42");
|
|
else if ( has_sse2() )
|
|
sprintf(outbuf, "SSE2");
|
|
else if ( has_sse() )
|
|
sprintf(outbuf, "SSE");
|
|
else
|
|
*outbuf = '\0';
|
|
|
|
#endif
|
|
}
|
|
|
|
static inline void cpu_brand_string( char* s )
|
|
{
|
|
#ifdef __arm__
|
|
sprintf( s, "ARM" );
|
|
#else
|
|
int cpu_info[4] = { 0 };
|
|
cpuid( VENDOR_ID, cpu_info );
|
|
if ( cpu_info[ EAX_Reg ] >= 4 )
|
|
{
|
|
cpuid( CPU_BRAND_1, cpu_info );
|
|
memcpy( s, cpu_info, sizeof(cpu_info) );
|
|
cpuid( CPU_BRAND_2, cpu_info );
|
|
memcpy( s + 16, cpu_info, sizeof(cpu_info) );
|
|
cpuid( CPU_BRAND_3, cpu_info );
|
|
memcpy( s + 32, cpu_info, sizeof(cpu_info) );
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#endif // SYSINFOS_C__
|
|
|