mirror of
https://github.com/JayDDee/cpuminer-opt.git
synced 2025-09-17 23:44:27 +00:00
711 lines
22 KiB
C
711 lines
22 KiB
C
#if !defined(SIMD_128_H__)
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#define SIMD_128_H__ 1
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#if defined(__SSE2__)
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///////////////////////////////////////////////////////////////////////////
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//
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// 128 bit SSE vectors
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//
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// SSE2 is required for 128 bit integer support. Some functions are also
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// optimized with SSSE3, SSE4.1 or AVX. Some of these more optimized
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// functions don't have SSE2 equivalents and their use would break SSE2
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// compatibility.
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//
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// Constants are an issue with simd. Simply put, immediate constants don't
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// exist. All simd constants either reside in memory or a register and
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// must be loaded from memory or generated at run time.
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//
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// Due to the cost of generating constants it is more efficient to
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// define a local const for repeated references to the same constant.
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//
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// One common use for simd constants is as a control index for vector
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// instructions like blend and shuffle. Alhough the ultimate instruction
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// may execute in a single clock cycle, generating the control index adds
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// several more cycles to the entire operation.
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//
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// All of the utilities here assume all data is in registers except
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// in rare cases where arguments are pointers.
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//
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// Some constants are generated using a memory overlay on the stack.
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//
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// Intrinsics automatically promote from REX to VEX when AVX is available
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// but ASM needs to be done manually.
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//
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///////////////////////////////////////////////////////////////////////////
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// Used instead if casting.
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typedef union
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{
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__m128i m128;
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uint32_t u32[4];
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} __attribute__ ((aligned (16))) m128_ovly;
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// Efficient and convenient moving between GP & low bits of XMM.
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// Use VEX when available to give access to xmm8-15 and zero extend for
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// larger vectors.
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static inline __m128i mm128_mov64_128( const uint64_t n )
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{
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__m128i a;
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#if defined(__AVX__)
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asm( "vmovq %1, %0\n\t" : "=x"(a) : "r"(n) );
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#else
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asm( "movq %1, %0\n\t" : "=x"(a) : "r"(n) );
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#endif
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return a;
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}
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static inline __m128i mm128_mov32_128( const uint32_t n )
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{
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__m128i a;
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#if defined(__AVX__)
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asm( "vmovd %1, %0\n\t" : "=x"(a) : "r"(n) );
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#else
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asm( "movd %1, %0\n\t" : "=x"(a) : "r"(n) );
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#endif
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return a;
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}
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// Inconstant naming, prefix should reflect return value:
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// u64_mov128_64
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static inline uint64_t u64_mov128_64( const __m128i a )
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{
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uint64_t n;
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#if defined(__AVX__)
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asm( "vmovq %1, %0\n\t" : "=r"(n) : "x"(a) );
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#else
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asm( "movq %1, %0\n\t" : "=r"(n) : "x"(a) );
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#endif
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return n;
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}
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static inline uint32_t u32_mov128_32( const __m128i a )
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{
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uint32_t n;
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#if defined(__AVX__)
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asm( "vmovd %1, %0\n\t" : "=r"(n) : "x"(a) );
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#else
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asm( "movd %1, %0\n\t" : "=r"(n) : "x"(a) );
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#endif
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return n;
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}
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// Equivalent of set1, broadcast integer to all elements.
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#define m128_const_i128( i ) mm128_mov64_128( i )
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#define m128_const1_64( i ) _mm_shuffle_epi32( mm128_mov64_128( i ), 0x44 )
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#define m128_const1_32( i ) _mm_shuffle_epi32( mm128_mov32_128( i ), 0x00 )
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#if defined(__SSE4_1__)
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// Assign 64 bit integers to respective elements: {hi, lo}
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#define m128_const_64( hi, lo ) \
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_mm_insert_epi64( mm128_mov64_128( lo ), hi, 1 )
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#else // No insert in SSE2
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#define m128_const_64 _mm_set_epi64x
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#endif
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// Pseudo constants
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#define m128_zero _mm_setzero_si128()
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#define m128_one_128 mm128_mov64_128( 1 )
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#define m128_one_64 _mm_shuffle_epi32( mm128_mov64_128( 1 ), 0x44 )
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#define m128_one_32 _mm_shuffle_epi32( mm128_mov32_128( 1 ), 0x00 )
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#define m128_one_16 _mm_shuffle_epi32( \
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mm128_mov32_128( 0x00010001 ), 0x00 )
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#define m128_one_8 _mm_shuffle_epi32( \
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mm128_mov32_128( 0x01010101 ), 0x00 )
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// ASM avoids the need to initialize return variable to avoid compiler warning.
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// Macro abstracts function parentheses to look like an identifier.
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static inline __m128i mm128_neg1_fn()
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{
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__m128i a;
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#if defined(__AVX__)
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asm( "vpcmpeqq %0, %0, %0\n\t" : "=x"(a) );
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#else
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asm( "pcmpeqq %0, %0\n\t" : "=x"(a) );
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#endif
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return a;
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}
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#define m128_neg1 mm128_neg1_fn()
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#if defined(__SSE4_1__)
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/////////////////////////////
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//
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// _mm_insert_ps( _mm128i v1, __m128i v2, imm8 c )
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//
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// Fast and powerful but very limited in its application.
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// It requires SSE4.1 but only works with 128 bit vectors with 32 bit
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// elements. There is no equivalent instruction for 256 bit or 512 bit vectors.
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// There's no integer version. There's no 64 bit, 16 bit or byte element
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// sizing. It's unique.
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//
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// It can:
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// - zero 32 bit elements of a 128 bit vector.
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// - extract any 32 bit element from one 128 bit vector and insert the
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// data to any 32 bit element of another 128 bit vector, or the same vector.
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// - do both simultaneoulsly.
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//
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// It can be used as a more efficient replacement for _mm_insert_epi32
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// or _mm_extract_epi32.
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//
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// Control byte definition:
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// c[3:0] zero mask
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// c[5:4] destination element selector
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// c[7:6] source element selector
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// Convert type and abbreviate name: e"x"tract "i"nsert "m"ask
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#define mm128_xim_32( v1, v2, c ) \
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_mm_castps_si128( _mm_insert_ps( _mm_castsi128_ps( v1 ), \
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_mm_castsi128_ps( v2 ), c ) )
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// Some examples of simple operations:
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// Insert 32 bit integer into v at element c and return modified v.
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static inline __m128i mm128_insert_32( const __m128i v, const uint32_t i,
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const int c )
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{ return mm128_xim_32( v, mm128_mov32_128( i ), c<<4 ); }
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// Extract 32 bit element c from v and return as integer.
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static inline uint32_t mm128_extract_32( const __m128i v, const int c )
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{ return u32_mov128_32( mm128_xim_32( v, v, c<<6 ) ); }
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// Clear (zero) 32 bit elements based on bits set in 4 bit mask.
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static inline __m128i mm128_mask_32( const __m128i v, const int m )
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{ return mm128_xim_32( v, v, m ); }
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// Move element i2 of v2 to element i1 of v1. For reference and convenience,
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// it's faster to precalculate the index.
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#define mm128_shuflmov_32( v1, i1, v2, i2 ) \
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mm128_xim_32( v1, v2, ( (i1)<<4 ) | ( (i2)<<6 ) )
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#endif // SSE4_1
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//
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// Basic operations without equivalent SIMD intrinsic
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// Bitwise not (~v)
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#define mm128_not( v ) _mm_xor_si128( v, m128_neg1 )
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// Unary negation of elements (-v)
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#define mm128_negate_64( v ) _mm_sub_epi64( m128_zero, v )
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#define mm128_negate_32( v ) _mm_sub_epi32( m128_zero, v )
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#define mm128_negate_16( v ) _mm_sub_epi16( m128_zero, v )
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// Add 4 values, fewer dependencies than sequential addition.
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#define mm128_add4_64( a, b, c, d ) \
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_mm_add_epi64( _mm_add_epi64( a, b ), _mm_add_epi64( c, d ) )
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#define mm128_add4_32( a, b, c, d ) \
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_mm_add_epi32( _mm_add_epi32( a, b ), _mm_add_epi32( c, d ) )
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#define mm128_add4_16( a, b, c, d ) \
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_mm_add_epi16( _mm_add_epi16( a, b ), _mm_add_epi16( c, d ) )
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#define mm128_add4_8( a, b, c, d ) \
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_mm_add_epi8( _mm_add_epi8( a, b ), _mm_add_epi8( c, d ) )
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#define mm128_xor4( a, b, c, d ) \
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_mm_xor_si128( _mm_xor_si128( a, b ), _mm_xor_si128( c, d ) )
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//
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// Vector pointer cast
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// p = any aligned pointer
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// returns p as pointer to vector type
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#define castp_m128i(p) ((__m128i*)(p))
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// p = any aligned pointer
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// returns *p, watch your pointer arithmetic
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#define cast_m128i(p) (*((__m128i*)(p)))
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// p = any aligned pointer, i = scaled array index
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// returns value p[i]
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#define casti_m128i(p,i) (((__m128i*)(p))[(i)])
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// p = any aligned pointer, o = scaled offset
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// returns pointer p+o
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#define casto_m128i(p,o) (((__m128i*)(p))+(o))
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// Memory functions
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// Mostly for convenience, avoids calculating bytes.
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// Assumes data is alinged and integral.
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// n = number of __m128i, bytes/16
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static inline void memset_zero_128( __m128i *dst, const int n )
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{ for ( int i = 0; i < n; i++ ) dst[i] = m128_zero; }
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static inline void memset_128( __m128i *dst, const __m128i a, const int n )
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{ for ( int i = 0; i < n; i++ ) dst[i] = a; }
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static inline void memcpy_128( __m128i *dst, const __m128i *src, const int n )
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{ for ( int i = 0; i < n; i ++ ) dst[i] = src[i]; }
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#if defined(__AVX512VL__)
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// a ^ b ^ c
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#define mm128_xor3( a, b, c ) \
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_mm_ternarylogic_epi64( a, b, c, 0x96 )
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// a ^ ( b & c )
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#define mm128_xorand( a, b, c ) \
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_mm_ternarylogic_epi64( a, b, c, 0x78 )
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#else
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#define mm128_xor3( a, b, c ) \
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_mm_xor_si128( a, _mm_xor_si128( b, c ) )
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#define mm128_xorand( a, b, c ) \
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_mm_xor_si128( a, _mm_and_si128( b, c ) )
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#endif
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// Mask making
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// Equivalent of AVX512 _mm_movepi64_mask & _mm_movepi32_mask.
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// Returns 2 or 4 bit integer mask from MSB of 64 or 32 bit elements.
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#define mm_movmask_64( v ) \
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_mm_castpd_si128( _mm_movmask_pd( _mm_castsi128_pd( v ) ) )
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#define mm_movmask_32( v ) \
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_mm_castps_si128( _mm_movmask_ps( _mm_castsi128_ps( v ) ) )
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// Diagonal blend
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// Blend 4 32 bit elements from 4 vectors
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#if defined (__AVX2__)
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#define mm128_diagonal_32( v3, v2, v1, v0 ) \
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mm_blend_epi32( _mm_blend_epi32( s3, s2, 0x4 ), \
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_mm_blend_epi32( s1, s0, 0x1 ), 0x3 )
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#elif defined(__SSE4_1__)
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#define mm128_diagonal_32( v3, v2, v1, v0 ) \
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mm_blend_epi16( _mm_blend_epi16( s3, s2, 0x30 ), \
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_mm_blend_epi16( s1, s0, 0x03 ), 0x0f )
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#endif
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//
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// Bit rotations
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// AVX512VL has implemented bit rotation for 128 bit vectors with
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// 64 and 32 bit elements.
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// x2 rotates elements in 2 individual vectors in a double buffered
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// optimization for SSE2, does nothing for AVX512 but is there for
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// transparency.
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// compiler doesn't like when a variable is used for the last arg of
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// _mm_rol_epi32, must be "8 bit immediate". Oddly _mm_slli has the same
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// specification but works with a variable. Therefore use rol_var where
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// necessary.
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// sm3-hash-4way.c has one instance where mm128_rol_var_32 is required.
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#define mm128_ror_var_64( v, c ) \
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_mm_or_si128( _mm_srli_epi64( v, c ), _mm_slli_epi64( v, 64-(c) ) )
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#define mm128_rol_var_64( v, c ) \
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_mm_or_si128( _mm_slli_epi64( v, c ), _mm_srli_epi64( v, 64-(c) ) )
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#define mm128_ror_var_32( v, c ) \
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_mm_or_si128( _mm_srli_epi32( v, c ), _mm_slli_epi32( v, 32-(c) ) )
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#define mm128_rol_var_32( v, c ) \
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_mm_or_si128( _mm_slli_epi32( v, c ), _mm_srli_epi32( v, 32-(c) ) )
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#if defined(__AVX512VL__)
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//#if defined(__AVX512F__) && defined(__AVX512VL__)
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#define mm128_ror_64 _mm_ror_epi64
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#define mm128_rol_64 _mm_rol_epi64
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#define mm128_ror_32 _mm_ror_epi32
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#define mm128_rol_32 _mm_rol_epi32
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#define mm128_rorx2_64( v1, v0, c ) \
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_mm_ror_epi64( v0, c ); \
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_mm_ror_epi64( v1, c )
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#define mm128_rolx2_64( v1, v0, c ) \
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_mm_rol_epi64( v0, c ); \
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_mm_rol_epi64( v1, c )
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#define mm128_rorx2_32( v1, v0, c ) \
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_mm_ror_epi32( v0, c ); \
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_mm_ror_epi32( v1, c )
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#define mm128_rolx2_32( v1, v0, c ) \
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_mm_rol_epi32( v0, c ); \
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_mm_rol_epi32( v1, c )
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#else // SSE2
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#define mm128_ror_64 mm128_ror_var_64
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#define mm128_rol_64 mm128_rol_var_64
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#define mm128_ror_32 mm128_ror_var_32
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#define mm128_rol_32 mm128_rol_var_32
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#define mm128_rorx2_64( v1, v0, c ) \
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{ \
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__m128i t0 = _mm_srli_epi64( v0, c ); \
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__m128i t1 = _mm_srli_epi64( v1, c ); \
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v0 = _mm_slli_epi64( v0, 64-(c) ); \
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v1 = _mm_slli_epi64( v1, 64-(c) ); \
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v0 = _mm_or_si256( v0, t0 ); \
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v1 = _mm_or_si256( v1, t1 ); \
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}
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#define mm128_rolx2_64( v1, v0, c ) \
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{ \
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__m128i t0 = _mm_slli_epi64( v0, c ); \
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__m128i t1 = _mm_slli_epi64( v1, c ); \
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v0 = _mm_srli_epi64( v0, 64-(c) ); \
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v1 = _mm_srli_epi64( v1, 64-(c) ); \
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v0 = _mm_or_si256( v0, t0 ); \
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v1 = _mm_or_si256( v1, t1 ); \
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}
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#define mm128_rorx2_32( v1, v0, c ) \
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{ \
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__m128i t0 = _mm_srli_epi32( v0, c ); \
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__m128i t1 = _mm_srli_epi32( v1, c ); \
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v0 = _mm_slli_epi32( v0, 32-(c) ); \
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v1 = _mm_slli_epi32( v1, 32-(c) ); \
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v0 = _mm_or_si256( v0, t0 ); \
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v1 = _mm_or_si256( v1, t1 ); \
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}
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#define mm128_rolx2_32( v1, v0, c ) \
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{ \
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__m128i t0 = _mm_slli_epi32( v0, c ); \
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__m128i t1 = _mm_slli_epi32( v1, c ); \
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v0 = _mm_srli_epi32( v0, 32-(c) ); \
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v1 = _mm_srli_epi32( v1, 32-(c) ); \
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v0 = _mm_or_si256( v0, t0 ); \
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v1 = _mm_or_si256( v1, t1 ); \
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}
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#endif // AVX512 else SSE2
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#define mm128_ror_16( v, c ) \
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_mm_or_si128( _mm_srli_epi16( v, c ), _mm_slli_epi16( v, 16-(c) ) )
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#define mm128_rol_16( v, c ) \
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_mm_or_si128( _mm_slli_epi16( v, c ), _mm_srli_epi16( v, 16-(c) ) )
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// Limited 2 input shuffle
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#define mm128_shuffle2_64( a, b, c ) \
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_mm_castpd_si128( _mm_shuffle_pd( _mm_castsi128_pd( a ), \
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_mm_castsi128_pd( b ), c ) );
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#define mm128_shuffle2_32( a, b, c ) \
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_mm_castps_si128( _mm_shuffle_ps( _mm_castsi128_ps( a ), \
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_mm_castsi128_ps( b ), c ) );
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//
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// Rotate vector elements accross all lanes
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#define mm128_swap_64( v ) _mm_shuffle_epi32( v, 0x4e )
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#define mm128_shuflr_64 mm128_swap_64
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#define mm128_shufll_64 mm128_swap_64
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#define mm128_shuflr_32( v ) _mm_shuffle_epi32( v, 0x39 )
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#define mm128_shufll_32( v ) _mm_shuffle_epi32( v, 0x93 )
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// Swap 32 bit elements in 64 bit lanes
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#define mm128_swap64_32( v ) _mm_shuffle_epi32( v, 0xb1 )
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#define mm128_shuflr64_32 mm128_swap64_32
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#define mm128_shufll64_32 mm128_swap64_32
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#if defined(__SSSE3__)
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// Rotate right by c bytes, no SSE2 equivalent.
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static inline __m128i mm128_shuflr_x8( const __m128i v, const int c )
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{ return _mm_alignr_epi8( v, v, c ); }
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//
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// Endian byte swap.
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#define mm128_bswap_64( v ) \
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_mm_shuffle_epi8( v, m128_const_64( 0x08090a0b0c0d0e0f, \
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0x0001020304050607 ) )
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#define mm128_bswap_32( v ) \
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_mm_shuffle_epi8( v, m128_const_64( 0x0c0d0e0f08090a0b, \
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0x0405060700010203 ) )
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#define mm128_bswap_16( v ) \
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_mm_shuffle_epi8( v, m128_const_64( 0x0e0f0c0d0a0b0809, \
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0x0607040502030001 )
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// 8 byte qword * 8 qwords * 2 lanes = 128 bytes
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#define mm128_block_bswap_64( d, s ) do \
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{ \
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__m128i ctl = m128_const_64( 0x08090a0b0c0d0e0f, 0x0001020304050607 ); \
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casti_m128i( d, 0 ) = _mm_shuffle_epi8( casti_m128i( s, 0 ), ctl ); \
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casti_m128i( d, 1 ) = _mm_shuffle_epi8( casti_m128i( s, 1 ), ctl ); \
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casti_m128i( d, 2 ) = _mm_shuffle_epi8( casti_m128i( s, 2 ), ctl ); \
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casti_m128i( d, 3 ) = _mm_shuffle_epi8( casti_m128i( s, 3 ), ctl ); \
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casti_m128i( d, 4 ) = _mm_shuffle_epi8( casti_m128i( s, 4 ), ctl ); \
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casti_m128i( d, 5 ) = _mm_shuffle_epi8( casti_m128i( s, 5 ), ctl ); \
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casti_m128i( d, 6 ) = _mm_shuffle_epi8( casti_m128i( s, 6 ), ctl ); \
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casti_m128i( d, 7 ) = _mm_shuffle_epi8( casti_m128i( s, 7 ), ctl ); \
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} while(0)
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// 4 byte dword * 8 dwords * 4 lanes = 128 bytes
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#define mm128_block_bswap_32( d, s ) do \
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{ \
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__m128i ctl = m128_const_64( 0x0c0d0e0f08090a0b, 0x0405060700010203 ); \
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casti_m128i( d, 0 ) = _mm_shuffle_epi8( casti_m128i( s, 0 ), ctl ); \
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casti_m128i( d, 1 ) = _mm_shuffle_epi8( casti_m128i( s, 1 ), ctl ); \
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casti_m128i( d, 2 ) = _mm_shuffle_epi8( casti_m128i( s, 2 ), ctl ); \
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casti_m128i( d, 3 ) = _mm_shuffle_epi8( casti_m128i( s, 3 ), ctl ); \
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casti_m128i( d, 4 ) = _mm_shuffle_epi8( casti_m128i( s, 4 ), ctl ); \
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casti_m128i( d, 5 ) = _mm_shuffle_epi8( casti_m128i( s, 5 ), ctl ); \
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casti_m128i( d, 6 ) = _mm_shuffle_epi8( casti_m128i( s, 6 ), ctl ); \
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casti_m128i( d, 7 ) = _mm_shuffle_epi8( casti_m128i( s, 7 ), ctl ); \
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} while(0)
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#else // SSE2
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static inline __m128i mm128_bswap_64( __m128i v )
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{
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v = _mm_or_si128( _mm_slli_epi16( v, 8 ), _mm_srli_epi16( v, 8 ) );
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v = _mm_shufflelo_epi16( v, _MM_SHUFFLE( 0, 1, 2, 3 ) );
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return _mm_shufflehi_epi16( v, _MM_SHUFFLE( 0, 1, 2, 3 ) );
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}
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static inline __m128i mm128_bswap_32( __m128i v )
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{
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v = _mm_or_si128( _mm_slli_epi16( v, 8 ), _mm_srli_epi16( v, 8 ) );
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v = _mm_shufflelo_epi16( v, _MM_SHUFFLE( 2, 3, 0, 1 ) );
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return _mm_shufflehi_epi16( v, _MM_SHUFFLE( 2, 3, 0, 1 ) );
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}
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static inline __m128i mm128_bswap_16( __m128i v )
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{
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return _mm_or_si128( _mm_slli_epi16( v, 8 ), _mm_srli_epi16( v, 8 ) );
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}
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static inline void mm128_block_bswap_64( __m128i *d, const __m128i *s )
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{
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d[0] = mm128_bswap_64( s[0] );
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d[1] = mm128_bswap_64( s[1] );
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d[2] = mm128_bswap_64( s[2] );
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d[3] = mm128_bswap_64( s[3] );
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d[4] = mm128_bswap_64( s[4] );
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d[5] = mm128_bswap_64( s[5] );
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d[6] = mm128_bswap_64( s[6] );
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d[7] = mm128_bswap_64( s[7] );
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}
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static inline void mm128_block_bswap_32( __m128i *d, const __m128i *s )
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{
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d[0] = mm128_bswap_32( s[0] );
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d[1] = mm128_bswap_32( s[1] );
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d[2] = mm128_bswap_32( s[2] );
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d[3] = mm128_bswap_32( s[3] );
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d[4] = mm128_bswap_32( s[4] );
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d[5] = mm128_bswap_32( s[5] );
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d[6] = mm128_bswap_32( s[6] );
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d[7] = mm128_bswap_32( s[7] );
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}
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#endif // SSSE3 else SSE2
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//
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// Rotate in place concatenated 128 bit vectors as one 256 bit vector.
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// Swap 128 bit vectorse.
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#define mm128_swap256_128( v1, v2 ) \
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v1 = _mm_xor_si128( v1, v2 ); \
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v2 = _mm_xor_si128( v1, v2 ); \
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v1 = _mm_xor_si128( v1, v2 );
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// Two input shuffle-rotate.
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// Concatenate v1 & v2 and rotate as one 256 bit vector.
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// Continue to use vror/vrol for now to avoid confusion with
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// shufl2r/shufl2l function macros available with AVX512.
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#if defined(__SSSE3__)
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// Function macro with two inputs and one output, inputs are preserved.
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// Two input functions are not available without SSSE3. Use procedure
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// macros below instead.
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#define mm128_shufl2r_64( v1, v2 ) _mm_alignr_epi8( v2, v1, 8 )
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#define mm128_shufl2l_64( v1, v2 ) _mm_alignr_epi8( v1, v2, 8 )
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#define mm128_shufl2r_32( v1, v2 ) _mm_alignr_epi8( v2, v1, 4 )
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#define mm128_shufl2l_32( v1, v2 ) _mm_alignr_epi8( v1, v2, 4 )
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#define mm128_shufl2r_16( v1, v2 ) _mm_alignr_epi8( v2, v1, 2 )
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#define mm128_shufl2l_16( v1, v2 ) _mm_alignr_epi8( v1, v2, 2 )
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#define mm128_shufl2r_8( v1, v2 ) _mm_alignr_epi8( v2, v1, 8 )
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#define mm128_shufl2l_8( v1, v2 ) _mm_alignr_epi8( v1, v2, 8 )
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// Procedure macros with 2 inputs and 2 outputs, inputs args are overwritten.
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// These macros retain the vrol/vror name for now to avoid
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// confusion with the shufl2r/shuffle2l function macros above.
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// These may be renamed to something like shufl2r2 for 2 nputs and
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// 2 outputs, ie SHUFfLe 2 inputs Right with 2 outputs.
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#define mm128_vror256_64( v1, v2 ) \
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do { \
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__m128i t = _mm_alignr_epi8( v1, v2, 8 ); \
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v1 = _mm_alignr_epi8( v2, v1, 8 ); \
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v2 = t; \
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} while(0)
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#define mm128_vrol256_64( v1, v2 ) \
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do { \
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__m128i t = _mm_alignr_epi8( v1, v2, 8 ); \
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v2 = _mm_alignr_epi8( v2, v1, 8 ); \
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v1 = t; \
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} while(0)
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#define mm128_vror256_32( v1, v2 ) \
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do { \
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__m128i t = _mm_alignr_epi8( v1, v2, 4 ); \
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v1 = _mm_alignr_epi8( v2, v1, 4 ); \
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v2 = t; \
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} while(0)
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#define mm128_vrol256_32( v1, v2 ) \
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do { \
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__m128i t = _mm_alignr_epi8( v1, v2, 12 ); \
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v2 = _mm_alignr_epi8( v2, v1, 12 ); \
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v1 = t; \
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} while(0)
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#define mm128_vror256_16( v1, v2 ) \
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do { \
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__m128i t = _mm_alignr_epi8( v1, v2, 2 ); \
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v1 = _mm_alignr_epi8( v2, v1, 2 ); \
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v2 = t; \
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} while(0)
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#define mm128_vrol256_16( v1, v2 ) \
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do { \
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__m128i t = _mm_alignr_epi8( v1, v2, 14 ); \
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v2 = _mm_alignr_epi8( v2, v1, 14 ); \
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v1 = t; \
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} while(0)
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#define mm128_vror256_8( v1, v2 ) \
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do { \
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__m128i t = _mm_alignr_epi8( v1, v2, 1 ); \
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v1 = _mm_alignr_epi8( v2, v1, 1 ); \
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v2 = t; \
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} while(0)
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#define mm128_vrol256_8( v1, v2 ) \
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do { \
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__m128i t = _mm_alignr_epi8( v1, v2, 15 ); \
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v2 = _mm_alignr_epi8( v2, v1, 15 ); \
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v1 = t; \
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} while(0)
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#else // SSE2
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#define mm128_vror256_64( v1, v2 ) \
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do { \
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|
__m128i t = _mm_or_si128( _mm_srli_si128( v1, 8 ), \
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_mm_slli_si128( v2, 8 ) ); \
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v2 = _mm_or_si128( _mm_srli_si128( v2, 8 ), \
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_mm_slli_si128( v1, 8 ) ); \
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v1 = t; \
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} while(0)
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#define mm128_vrol256_64( v1, v2 ) \
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do { \
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__m128i t = _mm_or_si128( _mm_slli_si128( v1, 8 ), \
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_mm_srli_si128( v2, 8 ) ); \
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v2 = _mm_or_si128( _mm_slli_si128( v2, 8 ), \
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_mm_srli_si128( v1, 8 ) ); \
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v1 = t; \
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} while(0)
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#define mm128_vror256_32( v1, v2 ) \
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do { \
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__m128i t = _mm_or_si128( _mm_srli_si128( v1, 4 ), \
|
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_mm_slli_si128( v2, 12 ) ); \
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v2 = _mm_or_si128( _mm_srli_si128( v2, 4 ), \
|
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_mm_slli_si128( v1, 12 ) ); \
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v1 = t; \
|
|
} while(0)
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|
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#define mm128_vrol256_32( v1, v2 ) \
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do { \
|
|
__m128i t = _mm_or_si128( _mm_slli_si128( v1, 4 ), \
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_mm_srli_si128( v2, 12 ) ); \
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v2 = _mm_or_si128( _mm_slli_si128( v2, 4 ), \
|
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_mm_srli_si128( v1, 12 ) ); \
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v1 = t; \
|
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} while(0)
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|
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#define mm128_vror256_16( v1, v2 ) \
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|
do { \
|
|
__m128i t = _mm_or_si128( _mm_srli_si128( v1, 2 ), \
|
|
_mm_slli_si128( v2, 14 ) ); \
|
|
v2 = _mm_or_si128( _mm_srli_si128( v2, 2 ), \
|
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_mm_slli_si128( v1, 14 ) ); \
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v1 = t; \
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} while(0)
|
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|
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#define mm128_vrol256_16( v1, v2 ) \
|
|
do { \
|
|
__m128i t = _mm_or_si128( _mm_slli_si128( v1, 2 ), \
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|
_mm_srli_si128( v2, 14 ) ); \
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v2 = _mm_or_si128( _mm_slli_si128( v2, 2 ), \
|
|
_mm_srli_si128( v1, 14 ) ); \
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v1 = t; \
|
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} while(0)
|
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|
|
#define mm128_vror256_8( v1, v2 ) \
|
|
do { \
|
|
__m128i t = _mm_or_si128( _mm_srli_si128( v1, 1 ), \
|
|
_mm_slli_si128( v2, 15 ) ); \
|
|
v2 = _mm_or_si128( _mm_srli_si128( v2, 1 ), \
|
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_mm_slli_si128( v1, 15 ) ); \
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v1 = t; \
|
|
} while(0)
|
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|
|
#define mm128_vrol256_8( v1, v2 ) \
|
|
do { \
|
|
__m128i t = _mm_or_si128( _mm_slli_si128( v1, 1 ), \
|
|
_mm_srli_si128( v2, 15 ) ); \
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|
v2 = _mm_or_si128( _mm_slli_si128( v2, 1 ), \
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_mm_srli_si128( v1, 15 ) ); \
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v1 = t; \
|
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} while(0)
|
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|
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#endif // SSE4.1 else SSE2
|
|
|
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#endif // __SSE2__
|
|
#endif // SIMD_128_H__
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