mirror of
https://github.com/JayDDee/cpuminer-opt.git
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519 lines
17 KiB
C
519 lines
17 KiB
C
#if !defined(SIMD_256_H__)
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#define SIMD_256_H__ 1
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//#if defined(__AVX2__)
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/////////////////////////////////////////////////////////////////////
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//
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// AVX2 256 bit vectors
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//
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// Basic support for 256 bit vectors is available with AVX but integer
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// support requires AVX2.
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// Some 256 bit vector utilities require AVX512 or have more efficient
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// AVX512 implementations. They will be selected automatically but their use
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// is limited because 256 bit vectors are less likely to be used when 512
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// is available.
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#if defined(__AVX__)
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// Used instead of casting.
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typedef union
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{
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__m256i m256;
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__m128i m128[2];
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uint64_t u64[4];
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uint32_t u32[8];
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} __attribute__ ((aligned (32))) m256_ovly;
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//
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// Pointer casting
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// p = any aligned pointer
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// returns p as pointer to vector type, not very useful
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#define castp_m256i(p) ((__m256i*)(p))
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// p = any aligned pointer
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// returns *p, watch your pointer arithmetic
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#define cast_m256i(p) (*((__m256i*)(p)))
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// p = any aligned pointer, i = scaled array index
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// returns value p[i]
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#define casti_m256i(p,i) (((__m256i*)(p))[(i)])
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// p = any aligned pointer, o = scaled offset
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// returns pointer p+o
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#define casto_m256i(p,o) (((__m256i*)(p))+(o))
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#endif
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#if defined(__AVX2__)
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// Move integer to low element of vector, other elements are set to zero.
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#define mm256_mov64_256( i ) _mm256_castsi128_si256( mm128_mov64_128( i ) )
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#define mm256_mov32_256( i ) _mm256_castsi128_si256( mm128_mov32_128( i ) )
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// Move low element of vector to integer.
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#define u64_mov256_64( v ) u64_mov128_64( _mm256_castsi256_si128( v ) )
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#define u32_mov256_32( v ) u32_mov128_32( _mm256_castsi256_si128( v ) )
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// deprecated
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//#define mm256_mov256_64 u64_mov256_64
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//#define mm256_mov256_32 u32_mov256_32
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// concatenate two 128 bit vectors into one 256 bit vector: { hi, lo }
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#define mm256_concat_128( hi, lo ) \
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_mm256_inserti128_si256( _mm256_castsi128_si256( lo ), hi, 1 )
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// Equivalent of set, move 64 bit integer constants to respective 64 bit
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// elements.
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static inline __m256i m256_const_64( const uint64_t i3, const uint64_t i2,
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const uint64_t i1, const uint64_t i0 )
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{
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union { __m256i m256i;
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uint64_t u64[4]; } v;
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v.u64[0] = i0; v.u64[1] = i1; v.u64[2] = i2; v.u64[3] = i3;
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return v.m256i;
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}
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// Equivalent of set1.
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// 128 bit vector argument
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#define m256_const1_128( v ) \
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_mm256_permute4x64_epi64( _mm256_castsi128_si256( v ), 0x44 )
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// 64 bit integer argument zero extended to 128 bits.
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#define m256_const1_i128( i ) m256_const1_128( mm128_mov64_128( i ) )
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#define m256_const1_64( i ) _mm256_broadcastq_epi64( mm128_mov64_128( i ) )
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#define m256_const1_32( i ) _mm256_broadcastd_epi32( mm128_mov32_128( i ) )
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#define m256_const1_16( i ) _mm256_broadcastw_epi16( mm128_mov32_128( i ) )
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#define m256_const1_8 ( i ) _mm256_broadcastb_epi8 ( mm128_mov32_128( i ) )
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#define m256_const2_64( i1, i0 ) \
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m256_const1_128( m128_const_64( i1, i0 ) )
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//
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// All SIMD constant macros are actually functions containing executable
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// code and therefore can't be used as compile time initializers.
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#define m256_zero _mm256_setzero_si256()
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#define m256_one_256 mm256_mov64_256( 1 )
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#define m256_one_128 m256_const1_i128( 1 )
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#define m256_one_64 _mm256_broadcastq_epi64( mm128_mov64_128( 1 ) )
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#define m256_one_32 _mm256_broadcastd_epi32( mm128_mov64_128( 1 ) )
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#define m256_one_16 _mm256_broadcastw_epi16( mm128_mov64_128( 1 ) )
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#define m256_one_8 _mm256_broadcastb_epi8 ( mm128_mov64_128( 1 ) )
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static inline __m256i mm256_neg1_fn()
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{
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__m256i v;
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asm( "vpcmpeqq %0, %0, %0\n\t" : "=x"(v) );
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return v;
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}
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#define m256_neg1 mm256_neg1_fn()
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// Consistent naming for similar operations.
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#define mm128_extr_lo128_256( v ) _mm256_castsi256_si128( v )
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#define mm128_extr_hi128_256( v ) _mm256_extracti128_si256( v, 1 )
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//
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// Memory functions
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// n = number of 256 bit (32 byte) vectors
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static inline void memset_zero_256( __m256i *dst, const int n )
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{ for ( int i = 0; i < n; i++ ) dst[i] = m256_zero; }
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static inline void memset_256( __m256i *dst, const __m256i a, const int n )
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{ for ( int i = 0; i < n; i++ ) dst[i] = a; }
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static inline void memcpy_256( __m256i *dst, const __m256i *src, const int n )
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{ for ( int i = 0; i < n; i ++ ) dst[i] = src[i]; }
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//
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// Basic operations without SIMD equivalent
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// Bitwise not ( ~v )
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#define mm256_not( v ) _mm256_xor_si256( v, m256_neg1 ) \
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// Unary negation of each element ( -v )
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#define mm256_negate_64( v ) _mm256_sub_epi64( m256_zero, v )
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#define mm256_negate_32( v ) _mm256_sub_epi32( m256_zero, v )
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#define mm256_negate_16( v ) _mm256_sub_epi16( m256_zero, v )
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// Add 4 values, fewer dependencies than sequential addition.
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#define mm256_add4_64( a, b, c, d ) \
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_mm256_add_epi64( _mm256_add_epi64( a, b ), _mm256_add_epi64( c, d ) )
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#define mm256_add4_32( a, b, c, d ) \
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_mm256_add_epi32( _mm256_add_epi32( a, b ), _mm256_add_epi32( c, d ) )
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#define mm256_add4_16( a, b, c, d ) \
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_mm256_add_epi16( _mm256_add_epi16( a, b ), _mm256_add_epi16( c, d ) )
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#define mm256_add4_8( a, b, c, d ) \
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_mm256_add_epi8( _mm256_add_epi8( a, b ), _mm256_add_epi8( c, d ) )
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#if defined(__AVX512VL__)
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// AVX512 has ternary logic that supports any 3 input boolean expression.
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// a ^ b ^ c
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#define mm256_xor3( a, b, c ) \
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_mm256_ternarylogic_epi64( a, b, c, 0x96 )
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// legacy convenience only
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#define mm256_xor4( a, b, c, d ) \
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_mm256_xor_si256( a, mm256_xor3( b, c, d ) )
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// a & b & c
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#define mm256_and3( a, b, c ) \
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_mm256_ternarylogic_epi64( a, b, c, 0x80 )
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// a | b | c
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#define mm256_or3( a, b, c ) \
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_mm256_ternarylogic_epi64( a, b, c, 0xfe )
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// a ^ ( b & c )
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#define mm256_xorand( a, b, c ) \
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_mm256_ternarylogic_epi64( a, b, c, 0x78 )
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// a & ( b ^ c )
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#define mm256_andxor( a, b, c ) \
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_mm256_ternarylogic_epi64( a, b, c, 0x60 )
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// a ^ ( b | c )
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#define mm256_xoror( a, b, c ) \
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_mm256_ternarylogic_epi64( a, b, c, 0x1e )
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// a ^ ( ~b & c )
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#define mm256_xorandnot( a, b, c ) \
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_mm256_ternarylogic_epi64( a, b, c, 0xd2 )
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// a | ( b & c )
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#define mm256_orand( a, b, c ) \
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_mm256_ternarylogic_epi64( a, b, c, 0xf8 )
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// ~( a ^ b ), same as (~a) ^ b
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#define mm256_xnor( a, b ) \
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_mm256_ternarylogic_epi64( a, b, b, 0x81 )
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#else
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#define mm256_xor3( a, b, c ) \
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_mm256_xor_si256( a, _mm256_xor_si256( b, c ) )
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#define mm256_xor4( a, b, c, d ) \
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_mm256_xor_si256( _mm256_xor_si256( a, b ), _mm256_xor_si256( c, d ) )
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#define mm256_and3( a, b, c ) \
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_mm256_and_si256( a, _mm256_and_si256( b, c ) )
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#define mm256_or3( a, b, c ) \
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_mm256_or_si256( a, _mm256_or_si256( b, c ) )
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#define mm256_xorand( a, b, c ) \
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_mm256_xor_si256( a, _mm256_and_si256( b, c ) )
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#define mm256_andxor( a, b, c ) \
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_mm256_and_si256( a, _mm256_xor_si256( b, c ))
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#define mm256_xoror( a, b, c ) \
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_mm256_xor_si256( a, _mm256_or_si256( b, c ) )
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#define mm256_xorandnot( a, b, c ) \
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_mm256_xor_si256( a, _mm256_andnot_si256( b, c ) )
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#define mm256_orand( a, b, c ) \
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_mm256_or_si256( a, _mm256_and_si256( b, c ) )
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#define mm256_xnor( a, b ) \
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mm256_not( _mm256_xor_si256( a, b ) )
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#endif
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// Mask making
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// Equivalent of AVX512 _mm256_movepi64_mask & _mm256_movepi32_mask.
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// Returns 4 or 8 bit integer mask from MSB of 64 or 32 bit elements.
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#define mm256_movmask_64( v ) \
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_mm256_castpd_si256( _mm256_movmask_pd( _mm256_castsi256_pd( v ) ) )
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#define mm256_movmask_32( v ) \
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_mm256_castps_si256( _mm256_movmask_ps( _mm256_castsi256_ps( v ) ) )
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// Diagonal blending
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// Blend 4 64 bit elements from 4 vectors
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#define mm256_diagonal_64( v3, v2, v1, v0 ) \
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mm256_blend_epi32( _mm256_blend_epi32( v3, v2, 0x30 ), \
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_mm256_blend_epi32( v1, v0, 0x03 ), 0x0f )
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// Blend 8 32 bit elements from 8 vectors
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#define mm256_diagonal_32( v7, v6, v5, v4, v3, v2, v1, v0 ) \
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_mm256_blend_epi32( \
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_mm256_blend_epi32( \
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_mm256_blend_epi32( v7, v6, 0x40 ), \
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_mm256_blend_epi32( v5, v4, 0x10 ) 0x30 ), \
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_mm256_blend_epi32( \
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_mm256_blend_epi32( v3, v2, 0x04) \
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_mm256_blend_epi32( v1, v0, 0x01 ), 0x03 ), 0x0f )
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// Blend 4 32 bit elements from each 128 bit lane.
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#define mm256_diagonal128_32( v3, v2, v1, v0 ) \
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_mm256_blend_epi32( \
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_mm256_blend_epi32( v3, v2, 0x44) \
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_mm256_blend_epi32( v1, v0, 0x11 ) )
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//
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// Bit rotations.
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//
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// The only bit shift for more than 64 bits is with __int128 which is slow.
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//
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// AVX512 has bit rotate for 256 bit vectors with 64 or 32 bit elements
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//
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// x2 rotates elements in 2 individual vectors in a double buffered
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// optimization for SSE2, does nothing for AVX512 but is there for
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// transparency.
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// compiler doesn't like when a variable is used for the last arg of
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// _mm_rol_epi32, must be "8 bit immediate". Therefore use rol_var where
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// necessary.
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#define mm256_ror_var_64( v, c ) \
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_mm256_or_si256( _mm256_srli_epi64( v, c ), \
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_mm256_slli_epi64( v, 64-(c) ) )
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#define mm256_rol_var_64( v, c ) \
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_mm256_or_si256( _mm256_slli_epi64( v, c ), \
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_mm256_srli_epi64( v, 64-(c) ) )
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#define mm256_ror_var_32( v, c ) \
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_mm256_or_si256( _mm256_srli_epi32( v, c ), \
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_mm256_slli_epi32( v, 32-(c) ) )
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#define mm256_rol_var_32( v, c ) \
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_mm256_or_si256( _mm256_slli_epi32( v, c ), \
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_mm256_srli_epi32( v, 32-(c) ) )
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// The spec says both F & VL are required, but just in case AMD
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// decides to implement ROL/R without AVX512F.
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#if defined(__AVX512VL__)
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//#if defined(__AVX512F__) && defined(__AVX512VL__)
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// AVX512, control must be 8 bit immediate.
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#define mm256_ror_64 _mm256_ror_epi64
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#define mm256_rol_64 _mm256_rol_epi64
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#define mm256_ror_32 _mm256_ror_epi32
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#define mm256_rol_32 _mm256_rol_epi32
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#define mm256_rorx2_64( v1, v0, c ) \
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_mm256_ror_epi64( v0, c ); \
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_mm256_ror_epi64( v1, c )
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#define mm256_rolx2_64( v1, v0, c ) \
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_mm256_rol_epi64( v0, c ); \
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_mm256_rol_epi64( v1, c )
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#define mm256_rorx2_32( v1, v0, c ) \
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_mm256_ror_epi32( v0, c ); \
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_mm256_ror_epi32( v1, c )
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#define mm256_rolx2_32( v1, v0, c ) \
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_mm256_rol_epi32( v0, c ); \
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_mm256_rol_epi32( v1, c )
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#else // AVX2
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#define mm256_ror_64 mm256_ror_var_64
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#define mm256_rol_64 mm256_rol_var_64
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#define mm256_ror_32 mm256_ror_var_32
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#define mm256_rol_32 mm256_rol_var_32
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#define mm256_rorx2_64( v1, v0, c ) \
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{ \
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__m256i t0 = _mm256_srli_epi64( v0, c ); \
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__m256i t1 = _mm256_srli_epi64( v1, c ); \
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v0 = _mm256_slli_epi64( v0, 64-(c) ); \
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v1 = _mm256_slli_epi64( v1, 64-(c) ); \
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v0 = _mm256_or_si256( v0, t0 ); \
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v1 = _mm256_or_si256( v1, t1 ); \
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}
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#define mm256_rolx2_64( v1, v0, c ) \
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{ \
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__m256i t0 = _mm256_slli_epi64( v0, c ); \
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__m256i t1 = _mm256_slli_epi64( v1, c ); \
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v0 = _mm256_srli_epi64( v0, 64-(c) ); \
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v1 = _mm256_srli_epi64( v1, 64-(c) ); \
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v0 = _mm256_or_si256( v0, t0 ); \
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v1 = _mm256_or_si256( v1, t1 ); \
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}
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#define mm256_rorx2_32( v1, v0, c ) \
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{ \
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__m256i t0 = _mm256_srli_epi32( v0, c ); \
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__m256i t1 = _mm256_srli_epi32( v1, c ); \
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v0 = _mm256_slli_epi32( v0, 32-(c) ); \
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v1 = _mm256_slli_epi32( v1, 32-(c) ); \
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v0 = _mm256_or_si256( v0, t0 ); \
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v1 = _mm256_or_si256( v1, t1 ); \
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}
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#define mm256_rolx2_32( v1, v0, c ) \
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{ \
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__m256i t0 = _mm256_slli_epi32( v0, c ); \
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__m256i t1 = _mm256_slli_epi32( v1, c ); \
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v0 = _mm256_srli_epi32( v0, 32-(c) ); \
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v1 = _mm256_srli_epi32( v1, 32-(c) ); \
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v0 = _mm256_or_si256( v0, t0 ); \
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v1 = _mm256_or_si256( v1, t1 ); \
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}
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#endif // AVX512 else AVX2
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#define mm256_ror_16( v, c ) \
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_mm256_or_si256( _mm256_srli_epi16( v, c ), \
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_mm256_slli_epi16( v, 16-(c) ) )
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#define mm256_rol_16( v, c ) \
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_mm256_or_si256( _mm256_slli_epi16( v, c ), \
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_mm256_srli_epi16( v, 16-(c) ) )
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//
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// Rotate elements accross all lanes.
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// Swap 128 bit elements in 256 bit vector.
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#define mm256_swap_128( v ) _mm256_permute4x64_epi64( v, 0x4e )
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#define mm256_shuflr_128 mm256_swap_128
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#define mm256_shufll_128 mm256_swap_128
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// Rotate 256 bit vector by one 64 bit element
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#define mm256_shuflr_64( v ) _mm256_permute4x64_epi64( v, 0x39 )
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#define mm256_shufll_64( v ) _mm256_permute4x64_epi64( v, 0x93 )
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// Rotate 256 bit vector by one 32 bit element.
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#define mm256_shuflr_32( v ) \
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_mm256_permutevar8x32_epi32( v, \
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m256_const_64( 0x0000000000000007, 0x0000000600000005, \
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0x0000000400000003, 0x0000000200000001 ) )
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#define mm256_shufll_32( v ) \
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_mm256_permutevar8x32_epi32( v, \
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m256_const_64( 0x0000000600000005, 0x0000000400000003, \
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0x0000000200000001, 0x0000000000000007 ) )
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//
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// Rotate elements within each 128 bit lane of 256 bit vector.
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// Limited 2 input shuffle
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#define mm256_shuffle2_64( a, b, c ) \
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_mm256_castpd_si256( _mm256_shuffle_pd( _mm256_castsi256_pd( a ), \
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_mm256_castsi256_pd( b ), c ) );
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#define mm256_shuffle2_32( a, b, c ) \
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_mm256_castps_si256( _mm256_shuffle_ps( _mm256_castsi256_ps( a ), \
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_mm256_castsi256_ps( b ), c ) );
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#define mm256_swap128_64( v ) _mm256_shuffle_epi32( v, 0x4e )
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#define mm256_shuflr128_64 mm256_swap128_64
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#define mm256_shufll128_64 mm256_swap128_64
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#define mm256_shuflr128_32( v ) _mm256_shuffle_epi32( v, 0x39 )
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#define mm256_shufll128_32( v ) _mm256_shuffle_epi32( v, 0x93 )
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static inline __m256i mm256_shuflr128_x8( const __m256i v, const int c )
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{ return _mm256_alignr_epi8( v, v, c ); }
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// Swap 32 bit elements in each 64 bit lane.
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#define mm256_swap64_32( v ) _mm256_shuffle_epi32( v, 0xb1 )
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#define mm256_shuflr64_32 mm256_swap64_32
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#define mm256_shufll64_32 mm256_swap64_32
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// NOTE: _mm256_shuffle_epi8, like most shuffles, is restricted to 128 bit
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// lanes. AVX512, however, supports full vector 8 bit shuffle. The AVX512VL +
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// AVX512BW intrinsic _mm256_mask_shuffle_epi8 with a NULL mask, can be used if
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// needed for a shuffle that crosses 128 bit lanes. BSWAP doesn't therefore the
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// AVX2 version will work here. The bswap control vector is coded to work
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// with both versions, bit 4 is ignored in AVX2.
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// Reverse byte order in elements, endian bswap.
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#define mm256_bswap_64( v ) \
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_mm256_shuffle_epi8( v, \
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m256_const_64( 0x18191a1b1c1d1e1f, 0x1011121314151617, \
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0x08090a0b0c0d0e0f, 0x0001020304050607 ) )
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#define mm256_bswap_32( v ) \
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_mm256_shuffle_epi8( v, \
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m256_const_64( 0x1c1d1e1f18191a1b, 0x1415161710111213, \
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0x0c0d0e0f08090a0b, 0x0405060700010203 ) )
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|
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#define mm256_bswap_16( v ) \
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_mm256_shuffle_epi8( v, \
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m256_const_64( 0x1e1f1c1d1a1b1819, 0x1617141512131011, \
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0x0e0f0c0d0a0b0809, 0x0607040502030001, ) )
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// Source and destination are pointers, may point to same memory.
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// 8 byte qword * 8 qwords * 4 lanes = 256 bytes
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#define mm256_block_bswap_64( d, s ) do \
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{ \
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__m256i ctl = m256_const_64( 0x18191a1b1c1d1e1f, 0x1011121314151617, \
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0x08090a0b0c0d0e0f, 0x0001020304050607 ) ; \
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casti_m256i( d, 0 ) = _mm256_shuffle_epi8( casti_m256i( s, 0 ), ctl ); \
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casti_m256i( d, 1 ) = _mm256_shuffle_epi8( casti_m256i( s, 1 ), ctl ); \
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casti_m256i( d, 2 ) = _mm256_shuffle_epi8( casti_m256i( s, 2 ), ctl ); \
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casti_m256i( d, 3 ) = _mm256_shuffle_epi8( casti_m256i( s, 3 ), ctl ); \
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casti_m256i( d, 4 ) = _mm256_shuffle_epi8( casti_m256i( s, 4 ), ctl ); \
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casti_m256i( d, 5 ) = _mm256_shuffle_epi8( casti_m256i( s, 5 ), ctl ); \
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casti_m256i( d, 6 ) = _mm256_shuffle_epi8( casti_m256i( s, 6 ), ctl ); \
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casti_m256i( d, 7 ) = _mm256_shuffle_epi8( casti_m256i( s, 7 ), ctl ); \
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} while(0)
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|
|
// 4 byte dword * 8 dwords * 8 lanes = 256 bytes
|
|
#define mm256_block_bswap_32( d, s ) do \
|
|
{ \
|
|
__m256i ctl = m256_const_64( 0x1c1d1e1f18191a1b, 0x1415161710111213, \
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|
0x0c0d0e0f08090a0b, 0x0405060700010203 ); \
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casti_m256i( d, 0 ) = _mm256_shuffle_epi8( casti_m256i( s, 0 ), ctl ); \
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casti_m256i( d, 1 ) = _mm256_shuffle_epi8( casti_m256i( s, 1 ), ctl ); \
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casti_m256i( d, 2 ) = _mm256_shuffle_epi8( casti_m256i( s, 2 ), ctl ); \
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casti_m256i( d, 3 ) = _mm256_shuffle_epi8( casti_m256i( s, 3 ), ctl ); \
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casti_m256i( d, 4 ) = _mm256_shuffle_epi8( casti_m256i( s, 4 ), ctl ); \
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|
casti_m256i( d, 5 ) = _mm256_shuffle_epi8( casti_m256i( s, 5 ), ctl ); \
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|
casti_m256i( d, 6 ) = _mm256_shuffle_epi8( casti_m256i( s, 6 ), ctl ); \
|
|
casti_m256i( d, 7 ) = _mm256_shuffle_epi8( casti_m256i( s, 7 ), ctl ); \
|
|
} while(0)
|
|
|
|
//
|
|
// Rotate two concatenated 256 bit vectors as one 512 bit vector by specified
|
|
// number of elements. Rotate is done in place, source arguments are
|
|
// overwritten.
|
|
// Some of these can use permute but appears to be slower. Maybe a Ryzen
|
|
// issue
|
|
|
|
// _mm256_alignr_epi 64/32 are only available with AVX512 but AVX512 also
|
|
// makes these macros unnecessary.
|
|
|
|
// continue using vror/vrol notation for now to avoid confusion with
|
|
// shufl2r/shufl2l macro functions available with AVX512.
|
|
#define mm256_swap512_256( v1, v2 ) \
|
|
v1 = _mm256_xor_si256( v1, v2 ); \
|
|
v2 = _mm256_xor_si256( v1, v2 ); \
|
|
v1 = _mm256_xor_si256( v1, v2 );
|
|
|
|
#endif // __AVX2__
|
|
#endif // SIMD_256_H__
|
|
|